Inventor
Jalil Fadavi-Ardekani
Inventor
Orefield, PA, US
Overview
Patents· 23 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing30%
H04LTransmission of digital information, e.g. telegraphic communication22%
H04MTelephonic communication14%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use14%
G11CStatic stores5%
G01RMeasuring electric variables3%
G06TImage data processing or generation, in general3%
G10HElectrophonic musical instruments3%
H03HImpedance networks, e.g. resonant circuits3%
H04NPictorial communication, e.g. television3%
PatentTitleYear
8,909,956'Method for managing and controlling the low power modes for an integrated circuit device'20147,739,528'Method for managing and controlling the low power modes for an integrated circuit device'20106,965,974'Dynamic partitioning of memory banks among multiple agents'20056,842,844'Parameter memory for hardware accelerator'20056,707,822'Multi-session asymmetric digital subscriber line buffering and scheduling apparatus and method'20046,499,087'Synchronous memory sharing based on cycle stealing'20026,496,916'System for flexible memory paging in partitioning memory'20026,401,176'Multiple agent use of a multi-ported shared memory'20026,297,751'Low-voltage joystick port interface'20016,279,048'System wake-up based on joystick movement'20016,275,948'Processor powerdown operation using intermittent bursts of instruction clock'20016,263,075'Interrupt mechanism using TDM serial interface'20016,243,459'Telephone with adaptive speed dial mechanism'20016,230,215'On-demand transfer engine'20016,189,076'Shared synchronous memory with a switching circuit controlled by an arbiter and method for glitch free switching of a clock signal'20016,108,371'System and method for writing mixed interleaved and non-interleaved data to a modem register'20006,067,317'Computer bus resource port'20005,928,317'Fast converter for left-to-right carry-free multiplier'19995,861,568'Generation of wave functions by storage of parameters for piecewise linear approximations'19995,754,590'Modem architecture for integrated controller and data pump applications'19985,694,444'Testable high count counter'19975,412,740'Signal processing system having reduced memory space'19955,117,291'Technique for adjusting signal dispersion cancellation apparatus in communications systems'1992Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1992Patents assigned to AT & T BELL LAB (1)· patent assignee history
1992–2005Based in Orefield, PA, US· patent location history
1997–2001Patents assigned to LUCENT TECHNOLOGIES INC (9)· patent assignee history
1999Based in Orefiled, PA, US· patent location history
2001–2002Patents assigned to AGERE SYST GUARDIAN CORP (6)· patent assignee history
2001–2014Based in Newport Coast, CA, US· patent location history
2002–2005Patents assigned to AGERE SYSTEMS INC (4)· patent assignee history
2010–2014Patents assigned to BROADCOM CORP (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| LUCENT TECHNOLOGIES INC | 9 | 1997–2001 |
| AGERE SYST GUARDIAN CORP | 6 | 2001–2002 |
| AGERE SYSTEMS INC | 4 | 2002–2005 |
| BROADCOM CORP | 2 | 2010–2014 |
| AT & T BELL LAB | 1 | 1992 |
Locations
| Location | Patents | Span |
|---|---|---|
| Orefield, Pennsylvania, US | 17 | 1992–2005 |
| Newport Coast, California, US | 5 | 2001–2014 |
| Orefiled, Pennsylvania, US | 1 | 1999 |