Inventor
Peter J. Geiss
Inventor
Underhill, VT, US
Overview
Patents· 25 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices57%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests12%
H10BElectronic memory devices10%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%
C30BSingle-crystal growth2%
PatentTitleYear
7,777,302'Method of controlling grain size in a polysilicon layer and in semiconductor devices having polysilicon structure'20107,696,034'Methods of base formation in a BiCOMS process'20107,625,792'Method of base formation in a BiCMOS process'20097,538,004'Method of fabrication for SiGe heterojunction bipolar transistor (HBT)'20097,491,985'Method of collector formation in BiCMOS technology'20097,390,721'Methods of base formation in a BiCMOS process'20087,317,215'SiGe heterojunction bipolar transistor (HBT)'20087,247,924'Method of controlling grain size in a polysilicon layer and in semiconductor devices having polysilicon structures'20077,002,190'Method of collector formation in BiCMOS technology'20066,967,167'Silicon dioxide removing method'20056,965,133'Method of base formation in a BiCMOS process'20056,936,509'STI pull-down to control SiGe facet growth'20056,911,681'Method of base formation in a BiCMOS process'20056,682,992'Method of controlling grain size in a polysilicon layer and in semiconductor devices having polysilicon structures'20046,674,102'Sti pull-down to control SiGe facet growth'20046,660,664'Structure and method for formation of a blocked silicide resistor'20036,541,336'Method of fabricating a bipolar transistor having a realigned emitter'20036,448,124'Method for epitaxial bipolar BiCMOS'20026,420,747'MOSCAP design for improved reliability'20026,399,976'Shrink-wrap collar for DRAM deep trenches'20026,258,695'Dislocation suppression by carbon incorporation'20016,069,049'Shrink-wrap collar from DRAM deep trenches'20005,635,419'Porous silicon trench and capacitor structures'19975,508,542'Porous silicon trench and capacitor structures'19965,356,837'Method of making epitaxial cobalt silicide using a thin metal underlayer'1994Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1994–2010Patents assigned to IBM (25)· patent assignee history
1994–2010Based in Underhill, VT, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 25 | 1994–2010 |
Locations
| Location | Patents | Span |
|---|---|---|
| Underhill, VT, US | 25 | 1994–2010 |