Inventor
Shinn-Sheng Yu
Inventor
Hsinchu, TW
Overview
Patents· 116 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G03Fprimary
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices48%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1021%
H01LSemiconductor devices8%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%
B82YSpecific uses or applications of nanostructures3%
H10DInorganic electric semiconductor devices3%
H01JElectric discharge tubes or discharge lamps2%
G06FElectric digital data processing2%
B29CShaping or joining of plastics1%
G02BOptical elements, systems or apparatus1%
PatentTitleYear
10,867,112Methods of making mask using transmission cross coefficient (TCC) matrix of lithography process optical system202010,866,525Method of manufacturing a semiconductor device and apparatus for manufacturing the semiconductor device202010,831,094Pellicle for EUV mask and fabrication thereof202010,747,097Mask with multilayer structure and manufacturing method by using the same202010,691,014Extreme ultraviolet lithography system, device, and method for printing low pattern density features202010,684,552Method to mitigate defect printability for ID pattern202010,520,806Pellicle for EUV mask and fabrication thereof201910,274,819EUV pellicle fabrication methods and structures thereof201910,276,372Method for integrated circuit patterning201910,168,611Mask with multilayer structure and manufacturing method by using the same201910,162,257Extreme ultraviolet lithography system, device, and method for printing low pattern density features201810,031,411Pellicle for EUV mask and fabrication thereof201810,007,174Extreme ultraviolet lithography process and mask20189,996,013Extreme ultraviolet lithography process and mask20189,964,850Method to mitigate defect printability for ID pattern20189,886,543'Method providing for asymmetric pupil configuration for an extreme ultraviolet lithography process'20189,869,934'Collector in an extreme ultraviolet lithography system with optimal air curtain protection'20189,869,939'Lithography process'20189,870,612'Method for repairing a mask'20189,829,785Extreme ultraviolet lithography process and mask20179,823,585'EUV focus monitoring systems and methods'20179,766,536'Mask with multilayer structure and manufacturing method by using the same'20179,760,015'Extreme ultraviolet lithography process'20179,748,133'Via definition scheme'20179,733,562'Extreme ultraviolet lithography process and mask'20179,726,983'Method to define multiple layer patterns with a single exposure by charged particle beam lithography'20179,728,408'Method of semiconductor integrated circuit fabrication'20179,709,884'EUV mask and manufacturing method by using the same'20179,690,186'Extreme ultraviolet lithography process and mask'20179,685,367'Photomask for forming multiple layer patterns with a single exposure'20179,664,999'Method of making an extreme ultraviolet pellicle'20179,640,397'Method of fabricating a semiconductor integrated circuit using a directed self-assembly block copolymer'20179,618,837'Extreme ultraviolet lithography process and mask with reduced shadow effect and enhanced intensity'20179,612,523'Structure and method for reflective-type mask'20179,612,531'Method of fabricating an integrated circuit with enhanced defect repairability'20179,588,419'Extreme ultraviolet light (EUV) photomasks and fabrication methods thereof'20179,575,412'Method and system for reducing pole imbalance by adjusting exposure intensity'20179,557,636'Extreme ultraviolet lithography mask and multilayer deposition method for fabricating same'20179,557,649'Assist feature for a photolithographic process'20179,535,334'Extreme ultraviolet lithography process to print low pattern density features'20179,535,316'Photomask with three states for forming multiple layer patterns with a single exposure'20179,529,249'Extreme ultraviolet lithography process and mask'20169,529,250'EUV mask with ITO absorber to suppress out of band radiation'20169,529,272'Extreme ultraviolet lithography process and mask'20169,488,905'Extreme ultraviolet lithography process and mask with reduced shadow effect and enhanced intensity'20169,448,491'Extreme ultraviolet lithography process and mask'20169,442,387'Extreme ultraviolet lithography process'20169,442,384'Extreme ultraviolet lithography process and mask'20169,442,365'Mask for extreme ultraviolet lithography and method of fabricating same'20169,442,368'Method of making an extreme ultraviolet pellicle'20169,417,534'Lithography method and structure for resolution enhancement with a two-state mask'20169,418,862'Method for integrated circuit patterning'20169,412,647'Via definition scheme'20169,405,195'Method to define multiple layer patterns with a single exposure by charged particle beam lithography'20169,377,693'Collector in an extreme ultraviolet lithography system with optimal air curtain protection'20169,377,696'Extreme ultraviolet lithography process and mask'20169,354,507'Extreme ultraviolet lithography process and mask'20169,316,900'Extreme ultraviolet lithography process and mask'20169,304,390'Extreme ultraviolet lithography process and mask'20169,285,671'Mask for use in lithography'20169,285,673'Assist feature for a photolithographic process'20169,280,046'Method of fabricating mask'20169,261,774'Extreme ultraviolet lithography process and mask with reduced shadow effect and enhanced intensity'20169,256,123'Method of making an extreme ultraviolet pellicle'20169,257,282'Method of semiconductor integrated circuit fabrication'20169,252,048'Metal and via definition scheme'20169,244,366'Extreme ultraviolet lithography process and mask'20169,229,326'Method for integrated circuit patterning'20169,223,197'Lithography and mask for resolution enhancement'20159,213,232'Reflective mask and method of making same'20159,195,135'Method for mask fabrication and repair'20159,182,659'Extreme ultraviolet lithography process and mask'20159,184,054'Method for integrated circuit patterning'20159,146,459'Extreme ultraviolet lithography process and mask'20159,134,604'Extreme ultraviolet (EUV) mask and method of fabricating the EUV mask'20159,122,166'Extreme ultraviolet lithography process and mask'20159,116,435'Extreme ultraviolet lithography mask'20159,091,947'Extreme ultraviolet light (EUV) photomasks and fabrication methods thereof'20159,081,288'Extreme ultraviolet (EUV) mask, method of fabricating the EUV mask and method of inspecting the EUV mask'20159,081,312'Method to define multiple layer patterns with a single exposure by E-beam lithography'20159,075,313'Multiple exposures in extreme ultraviolet lithography'20159,052,595'Lithography process'20159,046,781'Structure and method for reflective-type mask'20159,034,569'Extreme ultraviolet lithography process and mask'20158,877,409'Reflective mask and method of making same'20148,841,047'Extreme ultraviolet lithography process and mask'20148,828,625'Extreme ultraviolet lithography mask and multilayer deposition method for fabricating same'20148,791,024'Method to define multiple layer patterns using a single exposure'20148,785,084'Method for mask fabrication and repair'20148,765,330'Phase shift mask for extreme ultraviolet lithography and method of fabricating same'20148,663,878'Mask and method for forming the same'20148,628,897'Extreme ultraviolet lithography process and mask'20148,492,054'Mechanisms for patterning fine features'20138,241,823'Method of fabrication of a semiconductor device having reduced pitch'20128,039,179'Integrated circuit layout design'20118,027,529'System for improving critical dimension uniformity'20117,989,355'Method of pitch halving'20117,924,401'Seal ring arrangements for immersion lithography systems'20117,897,297'Method and system for optimizing intra-field critical dimension uniformity using a sacrificial twin mask'20117,862,962'Integrated circuit layout design'20117,777,884'Method and system for optimizing sub-nanometer critical dimension using pitch offset'20107,732,109'Method and system for improving critical dimension uniformity'20107,580,129'Method and system for improving accuracy of critical dimension metrology'20097,517,639'Seal ring arrangements for immersion lithography systems'20097,259,850'Approach to improve ellipsometer modeling accuracy for solving material optical constants N & K'20076,998,198'Contact hole printing by packing and unpacking'20066,991,895'Defocus-invariant exposure for regular patterns'20066,787,272'Assist feature for random, isolated, semi-dense, and other non-dense contacts'20046,784,005'Photoresist reflow for enhanced process window for random, isolated, semi-dense, and other non-dense contacts'20046,749,972'Optical proximity correction common process window maximization over varying feature pitch'20046,664,011'Hole printing by packing and unpacking using alternating phase-shifting masks'20036,492,073'Removal of line end shortening in microlithography and mask set for removal'20026,348,288'Resolution enhancement method for deep quarter micron technology'20026,316,152'OPC method to improve e-beam writing time'20016,251,745'Two-dimensional scaling method for determining the overlay error and overlay process window for integrated circuits'20015,894,350'Method of in line intra-field correction of overlay alignment'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (59)· patent assignee history
1999Based in Changhua County, TW· patent location history
2001–2007Based in Taichung, TW· patent location history
2009–2020Based in Hsinchu, TW· patent location history
2012–2014Patents assigned to YEN ANTHONY (9)· patent assignee history
2012–2014Patents assigned to YU SHINN-SHENG (9)· patent assignee history
2014Patents assigned to LU YEN-CHENG (5)· patent assignee history
2015–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (57)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG | 59 | 1999–2016 |
| TAIWAN SEMICONDUCTOR MFG CO LTD | 57 | 2015–2020 |
| YEN ANTHONY | 9 | 2012–2014 |
| YU SHINN-SHENGself | 9 | 2012–2014 |
| LU YEN-CHENG | 5 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu, TW | 104 | 2009–2020 |
| Taichung, TW | 11 | 2001–2007 |
| Changhua County, TW | 1 | 1999 |