Inventor
Charles E. May
Inventor
Austin, TX, US
Overview
Patents· 118 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices36%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1027%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1019%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests7%
G01JMeasurement of intensity, velocity, spectral content, polarisation, phase or pulse characteristics of infrared, visible or ultraviolet light1%
G01NInvestigating or analysing materials by determining their chemical or physical properties1%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%
H10BElectronic memory devices1%
B01JChemical or physical processes, e.g. catalysis or colloid chemistry1%
B24BMachines, devices, or processes for grinding or polishing1%
PatentTitleYear
9,087,945'Nanowires, nanowire junctions, and methods of making the same'20157,601,643'Arrangement and method for fabricating a semiconductor wafer'20097,582,566'Method for redirecting void diffusion away from vias in an integrated circuit design'20097,436,040'Method and apparatus for diverting void diffusion in integrated circuit conductors'20087,361,965'Method and apparatus for redirecting void diffusion away from vias in an integrated circuit design'20087,358,594'Method of forming a low k polymer E-beam printable mechanical support'20087,023,067'Bond pad design'20066,972,217'Low k polymer E-beam printable mechanical support'20056,967,177'Temperature control system'20056,875,693'Via and metal line interface capable of reducing the incidence of electro-migration induced voids'20056,743,688'High performance MOSFET with modulated channel gate thickness'20046,707,114'Semiconductor wafer arrangement of a semiconductor wafer'20046,654,226'Thermal low k dielectrics'20036,638,776'Thermal characterization compensation'20036,620,729'Ion beam dual damascene process'20036,566,244'Process for improving mechanical strength of layers of low k dielectric material'20036,560,504'Use of contamination-free manufacturing data in fault detection and classification as well as in run-to-run control'20036,544,829'Polysilicon gate salicidation'20036,531,364'Advanced fabrication technique to form ultra thin gate dielectric using a sacrificial polysilicon seed layer'20036,521,520'Semiconductor wafer arrangement and method of processing a semiconductor wafer'20036,495,881'Programmable read only memory in CMOS process flow'20026,482,075'Process for planarizing an isolation structure in a substrate'20026,451,657'Transistor with an ultra short channel length defined by a laterally diffused nitrogen implant'20026,452,412'Drop-in test structure and methodology for characterizing an integrated circuit process flow and topography'20026,432,812'Method of coupling capacitance reduction'20026,420,220'Method of forming electrode for high performance semiconductor devices'20026,410,967'Transistor having enhanced metal silicide and a self-aligned gate electrode'20026,403,445'Enhanced trench isolation structure'20026,362,510'Semiconductor topography having improved active device isolation and reduced dopant migration'20026,348,413'High pressure N2 RTA process for TiS2 formation'20026,338,992'Programmable read only memory in CMOS process flow'20026,323,561'Spacer formation for precise salicide formation'20016,323,524'Semiconductor device having a vertical active region and method of manufacture thereof'20016,323,519'Ultrathin, nitrogen-containing MOSFET sidewall spacers using low-temperature semiconductor fabrication process'20016,303,962'Dielectrically-isolated transistor with low-resistance metal source and drain formed using sacrificial source and drain structures'20016,294,397'Drop-in test structure and abbreviated integrated circuit process flow for characterizing production integrated circuit process flow, topography, and equipment'20016,281,132'Device and method for etching nitride spacers formed upon an integrated circuit gate conductor'20016,274,442'Transistor having a nitrogen incorporated epitaxially grown gate dielectric and method of making same'20016,268,634'Transistor with an ultra short channel length defined by a laterally diffused nitrogen implant'20016,268,637'Method of making air gap isolation by making a lateral EPI bridge for low K isolation advanced CMOS fabrication'20016,261,908'Buried local interconnect'20016,261,909'Semiconductor device having ultra shallow junctions and a reduced channel length and method for making same'20016,255,215'Semiconductor device having silicide layers formed using a collimated metal layer'20016,251,800'Ultrathin deposited gate dielectric formation using low-power, low-pressure PECVD for improved semiconductor device performance'20016,249,032'Semiconductor device having patterned metal layer over a polysilicon line and method of fabrication thereof'20016,245,638'Trench and gate dielectric formation for semiconductor devices'20016,242,317'High quality isolation structure formation'20016,242,273'Fractal filter applied to a contamination-free manufacturing signal to improve signal-to-noise ratios'20016,225,168'Semiconductor device having metal gate electrode and titanium or tantalum nitride gate dielectric barrier layer and process of fabrication thereof'20016,222,230'Method of making an elevated source/drain with enhanced graded sidewalls for transistor scaling integrated with spacer formation'20016,210,999'Method and test structure for low-temperature integration of high dielectric constant gate dielectrics into self-aligned semiconductor devices'20016,207,485'Integration of high K spacers for dual gate oxide channel fabrication technique'20016,207,544'Method of fabricating ultra thin nitride spacers and device incorporating same'20016,204,153'Argon doped epitaxial layers for inhibiting punchthrough within a semiconductor device'20016,194,768'High dielectric constant gate dielectric with an overlying tantalum gate conductor formed on a sidewall surface of a sacrificial structure'20016,188,106'MOSFET having a highly doped channel liner and a dopant seal to provide enhanced device properties'20016,184,986'Depositing a material of controlled, variable thickness across a surface for planarization of that surface'20016,169,006'Semiconductor device having grown oxide spacers and method of manufacture thereof'20016,168,958'Semiconductor structure having multiple thicknesses of high-K gate dielectrics and process of manufacture therefor'20016,162,687'Method of manufacturing semiconductor device having oxide-nitride gate insulating layer'20006,159,814'Spacer formation by poly stack dopant profile design'20006,159,804'Disposable sidewall oxidation fabrication method for making a transistor having an ultra short channel length'20006,160,300'Multi-layer gate conductor having a diffusion barrier in the bottom layer'20006,156,649'Method of forming uniform sheet resistivity salicide'20006,150,708'Advanced CMOS circuitry that utilizes both sides of a wafer surface for increased circuit density'20006,151,119'Apparatus and method for determining depth profile characteristics of a dopant material in a semiconductor device'20006,150,222'Method of making a high performance transistor with elevated spacer formation and self-aligned channel regions'20006,146,983'Method of making semiconductor device having sacrificial salicidation layer'20006,146,952'Semiconductor device having self-aligned asymmetric source/drain regions and method of fabrication thereof'20006,144,071'Ultrathin silicon nitride containing sidewall spacers for improved transistor performance'20006,140,674'Buried trench capacitor'20006,140,691'Trench isolation structure having a low K dielectric material isolated from a silicon-based substrate'20006,130,012'Ion beam milling to generate custom reticles'20006,127,234'Ultra shallow extension formation using disposable spacers'20006,127,235'Method for making asymmetrical gate oxide thickness in channel MOSFET region'20006,127,251'Semiconductor device with a reduced width gate dielectric and method of making same'20006,117,739'Semiconductor device with layered doped regions and methods of manufacture'20006,117,763'Method of manufacturing a semiconductor device with a low permittivity dielectric layer and contamination due to exposure to water'20006,114,229'Polysilicon gate electrode critical dimension and drive current control in MOS transistor fabrication'20006,100,173'Forming a self-aligned silicide gate conductor to a greater thickness than junction silicide structures using a dual-salicidation process'20006,096,643'Method of fabricating a semiconductor device having polysilicon line with extended silicide layer'20006,090,694'Local interconnect patterning and contact formation'20006,090,676'Process for making high performance MOSFET with scaled gate electrode thickness'20006,087,705'Trench isolation structure partially bound between a pair of low K dielectric structures'20006,084,280'Transistor having a metal silicide self-aligned to the gate'20006,080,676'Device and method for etching spacers formed upon an integrated circuit gate conductor'20006,077,749'Method of making dual channel gate oxide thickness for MOSFET transistor design'20006,078,078'V-gate transistor'20006,071,749'Process for forming a semiconductor device with controlled relative thicknesses of the active region and gate electrode'20006,067,154'Method and apparatus for the molecular identification of defects in semiconductor manufacturing using a radiation scattering technique such as raman spectroscopy'20006,063,679'Spacer formation for graded dopant profile having a triangular geometry'20006,051,863'Transistor gate conductor having sidewall surfaces upon which a spacer having a profile that substantially prevents silicide bridging is formed'20006,046,089'Selectively sized spacers'20006,044,203'Rapid thermal anneal system and method including improved temperature sensing and monitoring'20006,037,607'Structure for testing junction leakage of salicided devices fabricated using shallow trench and refill techniques'20006,033,921'Method for depositing a material of controlled, variable thickness across a surface for planarization of that surface'20006,030,875'Method for making semiconductor device having nitrogen-rich active region-channel interface'20006,008,109'Trench isolation structure having a low K dielectric encapsulated by oxide'19996,008,095'Process for formation of isolation trenches with high-K gate dielectrics'19996,005,285'Argon doped epitaxial layers for inhibiting punchthrough within a semiconductor device'19995,990,488'Useable drop-in strategy for correct electrical analysis of semiconductor devices'19995,981,363'Method and apparatus for high performance transistor devices'19995,981,357'Semiconductor trench isolation with improved planarization methodology'19995,981,368'Enhanced shallow junction design by polysilicon line width reduction using oxidation with integrated spacer formation'19995,963,803'Method of making N-channel and P-channel IGFETs with different gate thicknesses and spacer widths'19995,949,126'Trench isolation structure employing protective sidewall spacers upon exposed surfaces of the isolation trench'19995,950,106'Method of patterning a metal substrate using spin-on glass as a hard mask'19995,943,585'Trench isolation structure having low K dielectric spacers arranged upon an oxide liner incorporated with nitrogen'19995,915,195'Ion implantation process to improve the gate oxide quality at the edge of a shallow trench isolation structure'19995,913,106'Method for testing junction leakage of salicided devices fabricated using shallow trench and refill techniques'19995,912,493'Enhanced oxidation for spacer formation integrated with LDD implantation'19995,904,539'Semiconductor trench isolation process resulting in a silicon mesa having enhanced mechanical and electrical properties'19995,882,983'Trench isolation structure partially bound between a pair of low K dielectric structures'19995,846,862'Semiconductor device having a vertical active region and method of manufacture thereof'19985,759,871'Structure for testing junction leakage of salicided devices fabricated using shallow trench and refill techniques'19985,714,392'Rapid thermal anneal system and method including improved temperature sensing and monitoring'19984,218,280'Method of cross-linking polyvinyl alcohol and other water soluble resins'19803,939,048'Process for making anhydrous metal halides'1976Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1976–1980Patents assigned to NASA (2)· patent assignee history
1976–1980Based in Rocky River, OH, US· patent location history
1998–2004Patents assigned to ADVANCED MICRO DEVICES INC (91)· patent assignee history
1998–2004Based in Austin, TX, US· patent location history
1999–2009Based in Gresham, OR, US· patent location history
2001Patents assigned to ADVANCED MICRO SERVICES (1)· patent assignee history
2001Patents assigned to ADVANCED MICRON DEVICES INC (1)· patent assignee history
2002–2009Patents assigned to LSI LOGIC CORP (19)· patent assignee history
2008–2009Based in Fairview, OR, US· patent location history
2015Based in Lexington, KY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ADVANCED MICRO DEVICES INC | 91 | 1998–2004 |
| LSI LOGIC CORP | 19 | 2002–2009 |
| NASA | 2 | 1976–1980 |
| ADVANCED MICRO SERVICES | 1 | 2001 |
| ADVANCED MICRON DEVICES INC | 1 | 2001 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 72 | 1998–2004 |
| Gresham, OR, US | 40 | 1999–2009 |
| Fairview, OR, US | 3 | 2008–2009 |
| Rocky River, OH, US | 2 | 1976–1980 |
| Lexington, KY, US | 1 | 2015 |