Inventor

Renata Camillo-Castillo

Inventor

Essex Junction, VT, US

Overview

2010–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 54 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices38%

H01LSemiconductor devices29%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1013%

G06FElectric digital data processing4%

H01FMagnets1%

H01PWaveguides1%

H03FAmplifiers1%

Y02EReduction of greenhouse gas [ghg] emissions, related to energy generation, transmission or distribution1%

PatentTitleYear

10,784,346Extrinsic base doping for bipolar junction transistors2020 10,446,644Device structures for a silicon-on-insulator substrate with a high-resistance handle wafer2019 10,431,654Extrinsic base doping for bipolar junction transistors2019 10,367,083Compact device structures for a bipolar junction transistor2019 10,211,090Transistor with an airgap for reduced base-emitter capacitance and method of forming the transistor2019 10,170,553Shaped terminals for a bipolar junction transistor2019 10,164,101Transistor with improved channel mobility2018 10,153,361Heterojunction bipolar transistor device integration schemes on a same wafer2018 10,014,397Bipolar junction transistors with a combined vertical-lateral architecture2018 9,859,382'Integrated CMOS wafers'2018 9,825,157'Heterojunction bipolar transistor with stress component'2017 9,812,447'Bipolar junction transistors with extrinsic device regions free of trench isolation'2017 9,761,525'Multiple back gate transistor'2017 9,721,949'Method of forming super steep retrograde wells on FinFET'2017 9,722,057'Bipolar junction transistors with a buried dielectric region in the active device region'2017 9,653,566'Bipolar junction transistors with an air gap in the shallow trench isolation'2017 9,608,096'Implementing stress in a bipolar junction transistor'2017 9,583,569'Profile control over a collector of a bipolar junction transistor'2017 9,496,377'Self-aligned emitter-base-collector bipolar junction transistors with a single crystal raised extrinsic base'2016 9,368,608'Heterojunction bipolar transistor with improved performance and breakdown voltage'2016 9,324,846'Field plate in heterojunction bipolar transistor with improved break-down voltage'2016 9,318,551'Trench isolation structures and methods for bipolar junction transistors'2016 9,263,782'Notch filter structure with open stubs in semiconductor substrate and design structure'2016 9,257,324'Forming structures on resistive substrates'2016 9,245,951'Profile control over a collector of a bipolar junction transistor'2016 9,231,074'Bipolar junction transistors with an air gap in the shallow trench isolation'2016 9,224,858'Lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) with a below source isolation region and a method of forming the LDMOSFET'2015 9,219,128'Methods of fabricating bipolar junction transistors with reduced epitaxial base facets effect for low parasitic collector-base capacitance'2015 9,159,817'Heterojunction bipolar transistors with an airgap between the extrinsic base and collector'2015 9,159,801'Bipolar junction transistor with multiple emitter fingers'2015 9,111,986'Self-aligned emitter-base-collector bipolar junction transistors with a single crystal raised extrinsic base'2015 9,070,734'Heterojunction bipolar transistors with reduced parasitic capacitance'2015 9,059,138'Heterojunction bipolar transistor with reduced sub-collector length, method of manufacture and design structure'2015 9,034,712'Stress enhanced LDMOS transistor to minimize on-resistance and maintain high breakdown voltage'2015 8,975,146'Trench isolation structures and methods for bipolar junction transistors'2015 8,957,456'Heterojunction bipolar transistors with reduced parasitic capacitance'2015 8,946,799'Silicon controlled rectifier with stress-enhanced adjustable trigger voltage'2015 8,946,861'Bipolar device having a monocrystalline semiconductor intrinsic base to extrinsic base link-up region'2015 8,916,446'Bipolar junction transistor with multiple emitter fingers'2014 8,872,305'Integrated circuit structure having air-gap trench isolation and related design structure'2014 8,816,401'Heterojunction bipolar transistor'2014 8,809,998'Semiconductor device including in wafer inductors, related method and design structure'2014 8,810,005'Bipolar device having a monocrystalline semiconductor intrinsic base to extrinsic base link-up region'2014 8,735,986'Forming structures on resistive substrates'2014 8,716,837'Bipolar junction transistors with a link region connecting the intrinsic and extrinsic bases'2014 8,603,889'Integrated circuit structure having air-gap trench isolation and related design structure'2013 8,598,660'Stress enhanced LDMOS transistor to minimize on-resistance and maintain high breakdown voltage'2013 8,586,423'Silicon controlled rectifier with stress-enhanced adjustable trigger voltage'2013 8,536,012'Bipolar junction transistors with a link region connecting the intrinsic and extrinsic bases'2013 8,405,186'Transistor structure with a sidewall-defined intrinsic base to extrinsic base link-up region and method of forming the structure'2013 8,338,863'Vertical heterojunction bipolar transistors with reduced base-collector junction capacitance'2012 8,242,584'Structure and method to create stress trench'2012 8,232,156'Vertical heterojunction bipolar transistors with reduced base-collector junction capacitance'2012 7,791,105'Device structures for a high voltage junction field effect transistor manufactured using a hybrid orientation technology wafer and design structures for a high voltage integrated circuit'2010

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2010–2020Patents assigned to IBM (32)· patent assignee history

2010–2020Based in Essex Junction, VT, US· patent location history

2012–2015Patents assigned to CAMILLO-CASTILLO RENATA (9)· patent assignee history

2012–2015Patents assigned to LIU QIZHI (5)· patent assignee history

2013–2014Patents assigned to HARAME DAVID L (4)· patent assignee history

2015–2019Patents assigned to GLOBALFOUNDRIES INC (27)· patent assignee history

2017–2019Based in Williston, VT, US· patent location history

2019Based in Portland, OR, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	32	2010–2020
GLOBALFOUNDRIES INC	27	2015–2019
CAMILLO-CASTILLO RENATAself	9	2012–2015
LIU QIZHI	5	2012–2015
HARAME DAVID L	4	2013–2014

Locations

Location	Patents	Span
Essex Junction, VT, US	46	2010–2020
Williston, VT, US	7	2017–2019
Portland, OR, US	1	2019