LexDanaLexDanabeta
Inventor

Charles H. Dennison

Inventor
Meridian, ID, US

Overview

296→
Patents
1990–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 296 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Bprimary
H10BElectronic memory devices24%
H10DInorganic electric semiconductor devices23%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1017%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests15%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%
H10NElectric solid-state devices not otherwise provided for5%
G11CStatic stores4%
H01LSemiconductor devices2%
G06FElectric digital data processing1%
G01RMeasuring electric variables0%
PatentTitleYear
11,018,155Vertical string of memory cells individually comprising a programmable charge storage transistor comprising a control gate and a charge storage structure and method of forming a vertical string of memory cells individually comprising a programmable charge storage transistor comprising a control gate and a charge storage structure202110,877,352Semiconductor photonic devices using phase change materials202010,665,599Integrated structures and methods of forming vertically-stacked memory cells202010,622,374Vertical string of memory cells individually comprising a programmable charge storage transistor comprising a control gate and a charge storage structure and method of forming a vertical string of memory cells individually comprising a programmable charge storage transistor comprising a control gate and a charge storage structure202010,355,008Floating gate memory cells in vertical memory201910,269,819Integrated structures and methods of forming vertically-stacked memory cells201910,090,318Vertical string of memory cells individually comprising a programmable charge storage transistor comprising a control gate and a charge storage structure and method of forming a vertical string of memory cells individually comprising a programmable charge storage transistor comprising a control gate and a charge storage structure20189,991,273Floating gate memory cells in vertical memory20189,793,282'Floating gate memory cells in vertical memory'20179,754,952'Floating gate memory cells in vertical memory'20179,659,949'Integrated structures'20179,557,376'Apparatuses and methods for die seal crack detection'20179,287,184'Apparatuses and methods for die seal crack detection'20169,184,175'Floating gate memory cells in vertical memory'20158,699,267'Semiconductor phase change memory using face center cubic crystalline phase change material'20148,462,545'Semiconductor phase change memory using multiple phase change layers'20138,440,535'Forming a phase change memory with an ovonic threshold switch'20138,363,446'Multilevel variable resistance memory cell utilizing crystalline programming states'20138,223,538'Semiconductor phast change memory using multiple phase change layers'20128,188,454'Forming a phase change memory with an ovonic threshold switch'20128,098,519'Semiconductor phase change memory using multiple phase change layers'20128,097,514'Method for an integrated circuit contact'20128,067,761'Self-aligned memory cells and method for forming'20118,030,734'Forming phase change memories with a breakdown layer sandwiched by phase change memory material'20117,917,692'Method and system for using dynamic random access memory as cache memory'20117,871,934'Method for an integrated circuit contact'20117,838,341'Self-aligned memory cells and method for forming'20107,803,655'Method to manufacture a phase change memory'20107,804,082'Phase change memory system'20107,728,352'Damascene conductive line for contacting an underlying memory element'20107,729,162'Semiconductor phase change memory using multiple phase change layers'20107,572,666'Reduced area intersection between electrode and programming element'20097,569,485'Method for an integrated circuit contact'2009RE040790'Method for making electrical contact with an active area through sub-micron contact openings and a semiconductor device'20097,491,574'Reducing oxidation of phase change memory electrodes'20097,399,655'Damascene conductive line for contacting an underlying memory element'20087,390,691'Increasing phase change memory column landing margin'20087,359,227'Shared address lines for crosspoint memory'20087,355,203'Use of gate electrode workfunction to improve DRAM refresh'20087,348,268'Controlled breakdown phase change memory device'20087,350,018'Method and system for using dynamic random access memory as cache memory'20087,348,620'Forming phase change memories'20087,323,707'Initializing phase change memories'20087,315,082'Semiconductor device having integrated circuit contact'20087,314,776'Method to manufacture a phase change memory'20087,291,917'Integrated circuitry'20077,282,440'Integrated circuit contact'20077,282,447'Method for an integrated circuit contact'20077,276,448'Method for an integrated circuit contact'20077,274,049'Semiconductor assemblies'20077,229,887'Method to selectively remove one side of a conductive bottom electrode of a phase-change memory cell and structure obtained thereby'2007RE039665'Optimized container stacked capacitor DRAM cell utilizing sacrificial oxide deposition and chemical mechanical polishing'20077,217,945'Method to selectively increase the top resistance of the lower programming electrode in a phase-change memory cell and structures obtained thereby'20077,196,351'Forming phase change memories'20077,155,561'Method and system for using dynamic random access memory as cache memory'20067,119,397'Double blanket ion implant method and structure'20067,105,408'Phase change memory with a select device having a breakdown layer'20067,064,036'Dual-gate transistor device and method of forming a dual-gate transistor device'20067,005,666'Method to selectively increase the top resistance of the lower programming electrode in a phase-change memory cell and structures obtained thereby'20066,990,017'Accessing phase change memories'20066,969,633'Lower electrode isolation in a double-wide trench and method of making same'20056,967,146'Isolation region forming methods'20056,948,027'Method and system for using dynamic random access memory as cache memory'20056,939,799'Method of forming a field effect transistor and methods of forming integrated circuitry'20056,924,190'Use of gate electrode workfunction to improve DRAM refresh'20056,919,578'Utilizing atomic layer deposition for programmable device'20056,897,542'Semiconductor assemblies'20056,894,332'Apparatus for reducing electrical shorts from the bit line to the cell plate'20056,882,017'Field effect transistors and integrated circuitry'20056,869,883'Forming phase change memories'20056,862,654'Method and system for using dynamic random access memory as cache memory'20056,858,507'Graded LDD implant process for sub-half-micron MOS devices'20056,855,628'Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry'20056,833,291'Semiconductor processing methods'20046,818,496'Silicon on insulator DRAM process utilizing both fully and partially depleted devices'20046,808,982'Method of reducing electrical shorts from the bit line to the cell plate'20046,791,102'Phase change memory'20046,790,732'Self-aligned dual-gate transistor device and method of forming self-aligned dual-gate transistor device'20046,778,453'METHOD OF STORING A TEMPERATURE THRESHOLD IN AN INTEGRATED CIRCUIT, METHOD OF MODIFYING OPERATION OF DYNAMIC RANDOM ACCESS MEMORY IN RESPONSE TO TEMPERATURE, PROGRAMMABLE TEMPERATURE SENSING CIRCUIT AND MEMORY INTEGRATED CIRCUIT'20046,770,927'Structures comprising transistor gates'20046,759,285'Methods of forming transistors'20046,757,200'Semiconductor memory having dual port cell supporting hidden refresh'20046,753,241'Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry'20046,744,088'Phase change memory device on a planar composite layer'20046,710,420'Semiconductor construction of a trench'20046,696,355'Method to selectively increase the top resistance of the lower programming electrode in a phase-change memory'20046,693,014'Method of improving static refresh'20046,689,649'Methods of forming transistors'20046,677,650'Silicon plugs and local interconnect for embedded memory and system-on-chip (SOC) applications'20046,673,700'Reduced area intersection between electrode and programming element'20046,664,600'Graded LDD implant process for sub-half-micron MOS devices'20036,649,928'Method to selectively remove one side of a conductive bottom electrode of a phase-change memory cell and structure obtained thereby'20036,646,297'Lower electrode isolation in a double-wide trench'20036,620,672'SOI DRAM with buried capacitor under the digit lines utilizing a self aligning penetrating storage node contact formation'20036,605,527'Reduced area intersection between electrode and programming element'20036,605,532'Structure for an electrical contact to a thin film in a semiconductor structure and method for making the same'20036,593,206'Isolation region forming methods'20036,593,192'Method of forming a dual-gated semiconductor-on-insulator device'20036,593,176'METHOD FOR FORMING PHASE-CHANGE MEMORY BIPOLAR ARRAY UTILIZING A SINGLE SHALLOW TRENCH ISOLATION FOR CREATING AN INDIVIDUAL ACTIVE AREA REGION FOR TWO MEMORY ARRAY ELEMENTS AND ONE BIPOLAR BASE CONTACT'20036,573,601'Integrated circuit contact'20036,552,945'METHOD FOR STORING A TEMPERATURE THRESHOLD IN AN INTEGRATED CIRCUIT, METHOD FOR STORING A TEMPERATURE THRESHOLD IN A DYNAMIC RANDOM ACCESS MEMORY, METHOD OF MODIFYING DYNAMIC RANDOM ACCESS MEMORY OPERATION IN RESPONSE TO TEMPERATURE, PROGRAMMABLE TEMPERATURE SENSING CIRCUIT AND MEMORY INTEGRATED CIRCUIT'20036,552,401'Use of gate electrode workfunction to improve DRAM refresh'2003RE038049'Optimized container stacked capacitor dram cell utilizing sacrificial oxide deposition and chemical mechanical polishing'20036,537,891'Silicon on insulator DRAM process utilizing both fully and partially depleted devices'20036,534,781'Phase-change memory bipolar array utilizing a single shallow trench isolation for creating an individual active area region for two memory array elements and one bipolar base contact'20036,524,907'Method of reducing electrical shorts from the bit line to the cell plate'20036,511,867'Utilizing atomic layer deposition for programmable device'20036,501,114'Structures comprising transistor gates'20026,498,375'Integrated circuitry'20026,495,885'Graded LDD implant process for sub-half-micron MOS devices'20026,482,707'Method of improving static refresh'20026,479,332'Methods of forming integrated circuitry'20026,476,490'Contact openings, electrical connections and interconnections for integrated circuitry'20026,468,859'Method of reducing electrical shorts from the bit line to the cell plate'20026,468,883'Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections'20026,465,331'DRAM fabricated on a silicon-on-insulator (SOI) substrate having bi-level digit lines'2002RE037865'Semiconductor electrical interconnection methods'20026,448,141'Graded LDD implant process for sub-half-micron MOS devices'20026,444,520'Method of forming dual conductive plugs'20026,445,636'Method and system for hiding refreshes in a dynamic random access memory'20026,440,850'Structure for an electrical contact to a thin film in a semiconductor structure and method for making the same'20026,438,016'Semiconductor memory having dual port cell supporting hidden refresh'20026,429,069'SOI DRAM with buried capacitor under the digit lines utilizing a self aligning penetrating storage node contact formation'20026,420,250'Methods of forming portions of transistor structures, methods of forming array peripheral circuitry, and structures comprising transistor gates'20026,414,392'Integrated circuit contact'20026,410,951'Structure for improving static refresh'20026,406,977'Isolation region forming methods'20026,380,596'METHOD OF FORMING A LOCAL INTERCONNECT, METHOD OF FABRICATING INTEGRATED CIRCUITRY COMPRISING AN SRAM CELL HAVING A LOCAL INTERCONNECT AND HAVING CIRCUITRY PERIPHERAL TO THE SRAM CELL, AND METHOD OF FORMING CONTACT PLUGS'20026,376,358'Method of forming plugs and local interconnect for embedded memory/system-on-chip (SOC) applications'20026,376,287'Method of making field effect'20026,372,601'Isolation region forming methods'20026,358,787'Method of forming CMOS integrated circuitry'20026,350,638'Method of forming complementary type conductive regions on a substrate'20026,333,254'Methods of forming a local interconnect method of fabricating integrated circuitry comprising an SRAM cell having a local interconnect and having circuitry peripheral to the SRAM cell and method of forming contact plugs'20016,331,725'Integrated circuitry'20016,329,267'Isolation region forming methods'20016,323,087'Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry'20016,323,540'Semiconductor processing method of forming a contact opening to a region adjacent a field isolation mass, and a semiconductor structure'20016,312,984'Semiconductor processing method of forming a contact pedestal of forming a storage node of a capacitor and integrated circuitry'20016,307,226'Contact openings to electronic components having recessed sidewall structures'20016,306,696'Methods of forming integrated circuitry methods of forming thin film transistors, integrated circuitry and thin film transistors'20016,300,213'Semiconductor processing methods of forming a storage node of a capacitor'20016,291,871'Method of jointly forming stacked capacitors and antifuses, method of blowing antifuses, and antifuses and stacked capacitors constituting a part of integrated circuitry'20016,281,083'Methods of forming field effect transistor gates, and methods of forming integrated circuitry'20016,281,058'Method of forming DRAM circuitry on a semiconductor substrate'20016,271,126'Method of forming contact openings'20016,261,888'Method of forming CMOS integrated circuitry'20016,261,948'Method of forming contact openings'20016,251,714'Method of making thin film field effect transistors'20016,242,302'Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry'20016,238,999'Isolation region forming methods'20016,235,562'Method of making field effect transistors'20016,233,190'Method of storing a temperature threshold in an integrated circuit, method of modifying operation of dynamic random access memory in response to temperature, programmable temperature sensing circuit and memory integrated circuit'20016,229,212'Integrated circuitry and thin film transistors'20016,223,432'Method of forming dual conductive plugs'20016,221,729'Method of jointly forming stacked capacitors and antifuses, method of blowing antifuses, and antifuses and stacked capacitors constituting a part of integrated circuitry'20016,221,779'Self-aligned process for making contacts to silicon substrates during the manufacture of integrated circuits therein'2001RE037104'Planarization of a gate electrode for improved gate patterning over non-planar active area isolation'20016,200,842'Method of forming complementary type conductive regions on a substrate'20016,184,127'Semiconductor processing method of forming a contact opening to a region adjacent a field isolation mass, and a semiconductor structure'20016,184,096'Semiconductor processing method of providing dopant impurity into a semiconductor substrate'20016,180,450'Semiconductor processing methods of forming stacked capacitors'20016,159,813'Graded LDD implant process for sub-half-micron MOS devices'20006,150,201'Methods of forming top-gated thin film field effect transistors'20006,146,925'Method of jointly forming stacked capacitors and antifuses method of blowing antifuses method of blowing antifuses'20006,140,219'Method of forming contact openings'20006,124,616'Integrated circuitry comprising halo regions and LDD regions'20006,117,721'Semiconductor processing method of forming a static random access memory cell and static random access memory cell'20006,110,774'Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells'20006,107,145'Method for forming a field effect transistor'20006,100,144'Semiconductor processing method of providing electrical isolation between adjacent semiconductor diffusion regions of different field effect transistors and integrated circuitry having adjacent electrically isolated field effect transistors'20006,084,289'Semiconductor processing method of forming a contact opening to a region adjacent a field isolation mass, and a semiconductor structure'20006,083,831'Semiconductor processing method of forming a contact pedestal, of forming a storage node of a capacitor'20006,074,924'Method of forming CMOS integrated circuitry'20006,074,902'Method of forming complementary type conductive regions on a substrate'20006,049,093'Planar thin film transistor formation'2000RE036644'Tapered via, structures made therewith, and methods of producing same'20006,046,472'Graded LDD implant process for sub-half-micron MOS devices'20006,043,507'Thin film transistors and methods of making'20006,037,218'Semiconductor processing methods of forming stacked capacitors'20006,025,215'Method of making field effect transistors'2000RE036518'Method for making electrical contact with an active area through sub-micron contact openings and a semiconductor device'20006,004,854'Method of forming CMOS integrated circuitry'19996,002,149'Capacitor structures for memory cells'19995,970,335'Semiconductor processing method of forming complementary n-type doped and p-type doped active regions within a semiconductor substrate'1999RE036305'Method for fabrication of close-tolerance lines and sharp emission tips on a semiconductor wafer'19995,939,761'Method of forming a field effect transistor'19995,929,495'Semiconductor processing method of forming a static random access memory cell and static random access memory cell'19995,930,616'Methods of forming a field effect transistor and method of forming CMOS circuitry'19995,925,916'Semiconductor processing method of providing electrical isolation between adjacent semiconductor diffusion regions of different field effect transistors and integrated circuitry having adjacent electrically isolated field effect transistors'19995,923,965'Thin film transistors and method of making'19995,913,127'Method to thermally form hemispherical grain (HSG) silicon to enhance capacitance for application in high density DRAMS'19995,909,616'Method of forming CMOS circuitry'19995,904,532'Semiconductor processing method of providing dopant impurity into a semiconductor substrate'19995,900,660'Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory calls'19995,895,243'Semiconductor processing method of providing electrical isolation between adjacent semiconductor diffusion regions of different field effect transistors and integrated circuitry having adjacent electrically isolated field effect transistors'19995,888,877'Method of forming recessed container cells'19995,885,890'Method of forming contact openings and an electric component formed from the same and other methods'19995,872,059'Method of forming complementary type conductive regions on a substrate'19995,866,465'Semiconductor processing method of forming a contact opening to a region adjacent a field isolation mass'19995,858,821'Method of making thin film transistors'19995,858,877'Self-aligned process for making contacts to silicon substrates during the manufacture of integrated circuits therein'19995,847,406'Thin film field effect transistor'19985,844,254'Planar thin film transistor structures'19985,830,798'Method for forming a field effect transistor'19985,824,576'Method of forming complementary type conductive regions on a substrate'19985,821,140'Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells'19985,811,350'Method of forming contact openings and an electronic component formed from the same and other methods'19985,808,320'Contact openings and an electronic component formed from the same'19985,807,769'Methods of making thin film transistors'19985,801,087'Method of forming improved contacts from polysilicon to siliconor other polysilicon layers'19985,786,249'Method of forming dram circuitry on a semiconductor substrate'19985,780,326'Fully planarized thin film transistor (TFT) and process to fabricate same'19985,776,806'Method of forming CMOS integrated circuitry having halo regions'19985,756,393'Methods of jointly forming stacked capacitors and antifuses'19985,751,046'Semiconductor device with V.sub.T implant'19985,747,855'CMOS integrated circuitry with Halo and LDD regions'19985,739,056'Semiconductor processing method of forming a static random access memory cell and static random access memory cell'19985,736,437'Method of fabricating a bottom and top gated thin film transistor having an electrical sidewall connection'19985,733,809'Split-polysilicon CMOS process for multi-megabit dynamic memories incorporating stacked container capacitor cells'19985,726,483'Method of jointly forming stacked capacitors and antifuses, method of blowing antifuses, and antifuses and stacked capacitors constituting a part of integrated circuitry'19985,721,165'Method of forming CMOS circuitry'19985,719,424'Graded LDD implant process for sub-half-micron MOS devices'19985,705,838'Array of bit line over capacitor array of memory cells'19985,702,990'Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells'19975,700,730'Semiconductor processing method of providing dopant impurity into a semiconductor substrate'19975,691,547'Planar thin film transistor structures'19975,686,747'Integrated circuits comprising interconnecting plugs'19975,683,927'Method of forming CMOS integrated circuitry'19975,663,090'Method to thermally form hemispherical grain (HSG) silicon to enhance capacitance for application in high density DRAMs'19975,661,045'Method for forming and tailoring the electrical characteristics of semiconductor devices'19975,652,164'Semiconductor processing methods of forming stacked capacitors'19975,651,855'Method of making self aligned contacts to silicon substrates during the manufacture of integrated circuits'19975,650,350'Semiconductor processing method of forming a static random access memory cell and static random access memory cell'19975,650,655'Integrated circuitry having electrical interconnects'19975,637,525'Method of forming a CMOS circuitry'19975,624,863'Semiconductor processing method of forming complementary N-type doped and P-type doped active regions within a semiconductor substrate'19975,616,934'Fully planarized thin film transistor (TFT) and process to fabricate same'19975,605,857'Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells'19975,563,089'Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells'19965,541,137'Method of forming improved contacts from polysilicon to silicon or other polysilicon layers'19965,534,449'Methods of forming complementary metal oxide semiconductor (CMOS) integrated circuitry'19965,498,562'Semiconductor processing methods of forming stacked capacitors'19965,494,841'Split-polysilicon CMOS process for multi-megabit dynamic memories incorporating stacked container capacitor cells'19965,494,851'Semiconductor processing method of providing dopant impurity into a semiconductor substrate'19965,493,130'Integrated circuitry having an electrically conductive sidewall link positioned over and electrically interconnecting respective outer sidewalls of two conductive layers'19965,491,356'Capacitor structures for dynamic random access memory cells'19965,489,546'Method of forming CMOS devices using independent thickness spacers in a split-polysilicon DRAM process'19965,434,103'Method of forming an electrical connection'19955,411,909'Method of forming a planar thin film transistor'19955,405,788'Method for forming and tailoring the electrical characteristics of semiconductor devices'19955,401,681'Method of forming a bit line over capacitor array of memory cells'19955,397,908'Arrays of memory integrated circuitry'19955,393,683'Method of making semiconductor devices having two-layer gate structure'19955,391,511'Semiconductor processing method of producing an isolated polysilicon lined cavity and a method of forming a capacitor'19955,371,701'Stacked delta cell capacitor'19945,362,666'Method of producing a self-aligned contact penetrating cell plate'19945,348,899'Method of fabricating a bottom and top gated thin film transistor'19945,346,587'Planarization of a gate electrode for improved gate patterning over non-planar active area isolation'19945,340,763'Multi-pin stacked capacitor utilizing micro villus patterning in a container cell and method to fabricate same'19945,340,765'Method for forming enhanced capacitance stacked capacitor structures using hemi-spherical grain polysilicon'19945,338,700'Method of forming a bit line over capacitor array of memory cells'19945,334,862'Thin film transistor (TFT) loads formed in recessed plugs'19945,330,879'Method for fabrication of close-tolerance lines and sharp emission tips on a semiconductor wafer'19945,321,648'Stacked V-cell capacitor using a disposable outer digit line spacer'19945,321,649'Stacked delta cell capacitor'19945,292,683'Method of isolating semiconductor devices and arrays of memory integrated circuitry'19945,292,677'Reduced mask CMOS process for fabricating stacked capacitor multi-megabit dynamic random access memories utilizing single etch stop layer for contacts'19945,272,367'Fabrication of complementary n-channel and p-channel circuits (ICs) useful in the manufacture of dynamic random access memories (drams)'19935,270,241'Optimized container stacked capacitor DRAM cell utilizing sacrificial oxide deposition and chemical mechanical polishing'19935,266,513'Method of making stacked W-cell capacitor'19935,262,343'DRAM stacked capacitor fabrication process'19935,250,457'Method of forming a buried bit line array of memory cells'19935,244,837'Semiconductor electrical interconnection methods'19935,236,855'Stacked V-cell capacitor using a disposable outer digit line spacer'19935,234,855'Stacked comb spacer capacitor'19935,234,858'Stacked surrounding wall capacitor'19935,232,874'Method for producing a semiconductor wafer having shallow and deep buried contacts'19935,229,326'Method for making electrical contact with an active area through sub-micron contact openings and a semiconductor device'19935,219,778'Stacked V-cell capacitor'19935,206,183'Method of forming a bit line over capacitor array of memory cells'19935,198,384'Process for manufacturing a ferroelectric dynamic/non-volatile memory array using a disposable layer above storage-node junction'19935,196,364'Method of making a stacked capacitor dram cell'19935,170,233'Method for increasing capacitive surface area of a conductive material in semiconductor processing and stacked memory cell capacitor'19925,162,248'Optimized container stacked capacitor DRAM cell utilizing sacrificial oxide deposition and chemical mechanical polishing'19925,155,057'Stacked v-cell capacitor using a disposable composite dielectric on top of a digit line'19925,100,825'Method of making stacked surrounding reintrant wall capacitor'19925,100,838'Method for forming self-aligned conducting pillars in an (IC) fabrication process'19925,100,826'Process for manufacturing ultra-dense dynamic random access memories using partially-disposable dielectric filler strips between wordlines'19925,084,406'Method for forming low resistance DRAM digit-line'19925,061,650'Method for formation of a stacked capacitor'19915,053,351'Method of making stacked E-cell capacitor DRAM cell'19915,049,517'Method for formation of a stacked capacitor'19915,013,680'Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography'19914,981,810'Process for creating field effect transistors having reduced-slope, staircase-profile sidewall spacers'19914,965,221'Spacer isolation method for minimizing parasitic sidewall capacitance and creating fully recessed field oxide regions'1990

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1990–2021Patents assigned to MICRON TECHNOLOGY INC (238)· patent assignee history
1990–2014Based in Boise, ID, US· patent location history
1993–1996Patents assigned to MICRON SEMICONDUCTOR INC (10)· patent assignee history
1996–2021Based in Meridian, ID, US· patent location history
2001–2020Based in San Jose, CA, US· patent location history
2003–2014Patents assigned to OVONYX INC (26)· patent assignee history
2003–2020Patents assigned to INTEL CORP (14)· patent assignee history
2004Based in Santa Clara, CA, US· patent location history
2009–2013Patents assigned to DENNISON CHARLES H (8)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MICRON TECHNOLOGY INC2381990–2021
OVONYX INC262003–2014
INTEL CORP142003–2020
MICRON SEMICONDUCTOR INC101993–1996
DENNISON CHARLES Hself82009–2013
Locations
LocationPatentsSpan
Meridian, ID, US1241996–2021
Boise, ID, US1011990–2014
San Jose, California, US702001–2020
Santa Clara, California, US12004