Inventor
Stephen W. Bedell
Inventor
Wappingers Falls, NY, US
Overview
Patents· 314 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1017%
H01LSemiconductor devices17%
H10DInorganic electric semiconductor devices14%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1011%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation8%
Y02EReduction of greenhouse gas [ghg] emissions, related to energy generation, transmission or distribution8%
H10HInorganic light-emitting semiconductor devices having potential barriers4%
Y02PClimate change mitigation technologies in the production or processing of goods4%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
Y10TTechnical subjects covered by former us classification2%
PatentTitleYear
11,121,319Phase-change memory with no drift202111,107,966Two-sided Majorana fermion quantum computing devices fabricated with ion implant methods202111,107,965Majorana fermion quantum computing devices fabricated with ion implant methods202111,094,843High voltage photovoltaics integrated with light emitting diode containing zinc oxide containing layer202111,094,842Heterojunction photovoltaic device and fabrication method202111,068,777Voltage controlled highly linear resistive elements202111,062,204Voltage controlled highly linear resistive elements202111,063,161Monolithically integrated high voltage photovoltaics with textured surface formed during the growth of wide bandgap materials202111,055,612Voltage controlled highly linear resistive elements202111,031,631Fabrication of all-solid-state energy storage devices202111,003,942Electron channeling pattern acquisition from small crystalline areas202110,978,631Combined dolan bridge and quantum dot josephson junction in series202110,971,626Interface charge reduction for SiGe surface202110,957,806Monolithically integrated high voltage photovoltaics with textured surface formed during the growth of wide bandgap materials202110,943,169Battery-based neural network weights202110,923,458Vertical light emitting diode with magnetic back contact202110,898,725Integrated optogenetic device with light-emitting diodes and glass-like carbon electrodes202110,892,333Method of making a gallium nitride device202110,833,175Formation of dislocation-free SiGe finFET using porous silicon202010,833,311Method of making an anode structure containing a porous region202010,777,842Rechargeable lithium-ion battery with an anode structure containing a porous region202010,770,614Monolithically integrated high voltage photovoltaics and light emitting diode with textured surface202010,755,925Post growth heteroepitaxial layer separation for defect reduction in heteroepitaxial films202010,741,387High percentage silicon germanium graded buffer layers with lattice matched Ga(As202010,714,303Enabling high throughput electron channeling contrast imaging (ECCI) by varying electron beam energy202010,686,090Wafer bonded solar cells and fabrication methods202010,672,865Deformable and flexible capacitor202010,672,929Heterojunction photovoltaic device and fabrication method202010,658,531Spalling techniques for manufacturing photodiodes202010,644,110Co-integration of elastic and plastic relaxation on the same wafer202010,644,109Digital alloy vertical lamellae FinFET with current flow in alloy layer direction202010,644,184Type IV semiconductor based high voltage laterally stacked multijunction photovoltaic cell202010,636,837Solution deposited magnetically guided chiplet displacement202010,622,636High-capacity rechargeable battery stacks containing a spalled cathode material202010,601,033High-performance rechargeable batteries having a spalled and textured cathode layer202010,585,063Superhydrophobic electrode and biosensing device using the same202010,580,925High voltage photovoltaics integrated with light emitting diode containing zinc oxide containing layer202010,573,625Vertical light emitting diode with magnetic back contact202010,574,354Data transfer arrangement for a hybrid integrated circuit (HIC) and an HIC with the data transfer arrangement202010,566,493Device with integration of light-emitting diode, light sensor, and bio-electrode sensors on a substrate202010,559,555Micro-LED array transfer202010,541,343Monolithic integration of heterojunction solar cells202010,460,937Post growth heteroepitaxial layer separation for defect reduction in heteroepitaxial films201910,453,683Post growth heteroepitaxial layer separation for defect reduction in heteroepitaxial films201910,438,858Low-cost SOI FinFET technology201910,424,644Method of making a gallium nitride device201910,417,519Electron channeling pattern acquisition from small crystalline areas201910,396,182Silicon germanium-on-insulator formation by thermal mixing201910,396,061Transparent electronics for invisible smart dust applications201910,381,479Interface charge reduction for SiGe surface201910,365,240Flexible and stretchable sensors formed by patterned spalling201910,355,164Monolithically integrated high voltage photovoltaics and light emitting diode with textured surface201910,319,893Magnetically guided chiplet displacement201910,304,984Heterojunction photovoltaic device and fabrication method201910,304,985Heterojunction photovoltaic device and fabrication method201910,304,988High voltage photovoltaics integrated with light emitting diode201910,297,665Co-integration of elastic and plastic relaxation on the same wafer201910,276,739High voltage photovoltaics integrated with light emitting diode201910,256,357Monolithic integration of heterojunction solar cells201910,256,365Monolithically integrated high voltage photovoltaics and light emitting diode with textured surface201910,249,737Silicon germanium-on-insulator formation by thermal mixing201910,249,782High voltage photovoltaics integrated with light emitting diode containing zinc oxide containing layer201910,249,792Protective capping layer for spalled gallium nitride201910,249,783High voltage photovoltaics integrated with light emitting diode containing zinc oxide containing layer201910,204,823Enhancing robustness of SOI substrate containing a buried N201910,175,192Superhydrophobic electrode and biosensing device using the same201910,170,660Digital alloy germanium heterojunction solar cell201910,170,302Superlattice lateral bipolar junction transistor201910,170,311Method for handling thin brittle films201910,134,831Deformable and flexible capacitor201810,127,649Electron channeling pattern acquisition from small crystalline areas201810,115,711Vertical light emitting diode with magnetic back contact201810,083,850Method of forming a flexible semiconductor layer and devices on a flexible carrier201810,079,341Three-terminal non-volatile multi-state memory for cognitive computing applications201810,074,720Digital alloy vertical lamellae finfet with current flow in alloy layer direction201810,032,973Magnetically guided chiplet displacement201810,026,618Method for improving quality of spalled material layers201810,020,418Simplified process for vertical LED manufacturing201810,002,856Micro-LED array transfer20189,991,408Monolithically integrated high voltage photovoltaics and light emitting diode with textured surface20189,984,871Superlattice lateral bipolar junction transistor20189,984,941Non-destructive, wafer scale method to evaluate defect density in heterogeneous epitaxial layers20189,985,164Monolithically integrated high voltage photovoltaics and light emitting diode with textured surface20189,958,390On-chip molecule fluorescence detection20189,941,355Co-integration of elastic and plastic relaxation on the same wafer20189,935,223Monolithic integration of heterojunction solar cells20189,935,185Superlattice lateral bipolar junction transistor20189,935,230Type IV semiconductor based high voltage laterally stacked multijunction photovoltaic cell20189,929,313'Protective capping layer for spalled gallium nitride'20189,922,866'Enhancing robustness of SOI substrate containing a buried N+ silicon layer for CMOS processing'20189,918,382'Patterned metallization handle layer for controlled spalling'20189,899,274'Low-cost SOI FinFET technology'20189,874,534Flexible and stretchable sensors formed by patterned spalling20189,865,769'Back contact LED through spalling'20189,859,091'Automatic alignment for high throughput electron channeling contrast imaging'20189,818,901'Wafer bonded solar cells and fabrication methods'20179,818,761'Selective oxidation for making relaxed silicon germanium on insulator structures'20179,799,675'Strain engineering in back end of the line'20179,793,114'Uniform height tall fins with varying silicon germanium concentrations'20179,793,263'Digital alloy FinFET co-integrated with passive resistor with good temperature coefficient'20179,748,353'Method of making a gallium nitride device'20179,741,532'Multi-beam electron microscope for electron channeling contrast imaging of semiconductor material'20179,739,728'Automatic defect detection and classification for high throughput electron channeling contrast imaging'20179,741,897'Thin light emitting diode and fabrication method'20179,726,634'Superhydrophobic electrode and biosensing device using the same'20179,722,039'Fabricating high-power devices'20179,713,250'Patterned metallization handle layer for controlled spalling'20179,704,736'Method of forming a flexible semiconductor layer and devices on a flexible carrier'20179,698,039'Controlled spalling utilizing vaporizable release layers'20179,691,653'Method of forming a flexible semiconductor layer and devices on a flexible carrier'20179,679,972'Thin strain relaxed buffers with multilayer film stacks'20179,679,772'Method for handling thin brittle films'20179,666,669'Superlattice lateral bipolar junction transistor'20179,666,742'Solar cell structures having III-V base layers'20179,659,807'Method of forming a flexible semiconductor layer and devices on a flexible carrier'20179,607,854'Methods to reduce debonding forces on flexible semiconductor films disposed on vapor-releasing adhesives'20179,601,624'SOI based FINFET with strained source-drain regions'20179,578,736'Patterned metallization handle layer for controlled spalling'20179,576,837'Method of forming a flexible semiconductor layer and devices on a flexible carrier'20179,570,295'Protective capping layer for spalled gallium nitride'20179,570,485'Solar-powered energy-autonomous silicon-on-insulator device'20179,564,335'Method for improving quality of spalled material layers'20179,553,008'Methods to reduce debonding forces on flexible semiconductor films disposed on vapor-releasing adhesives'20179,548,235'Methods to reduce debonding forces on flexible semiconductor films disposed on vapor-releasing adhesives'20179,536,736'Reducing substrate bowing caused by high percentage sige layers'20179,513,220'On-chip molecule fluorescence detection'20169,502,609'Simplified process for vertical LED manufacturing'20169,502,540'Uniform height tall fins with varying silicon germanium concentrations'20169,502,278'Substrate holder assembly for controlled layer transfer'20169,502,420'Structure and method for highly strained germanium channel fins for high mobility pFINFETs'20169,496,165'Method of forming a flexible semiconductor layer and devices on a flexible carrier'20169,496,186'Uniform height tall fins with varying silicon germanium concentrations'20169,496,128'Controlled spalling utilizing vaporizable release layers'20169,484,209'Flexible and stretchable sensors formed by patterned spalling'20169,478,651'Breakdown voltage multiplying integration scheme'20169,472,703'Monolithic integration of heterojunction solar cells'20169,472,411'Spalling using dissolvable release layer'20169,466,651'Flexible active matrix display'20169,455,179'Methods to reduce debonding forces on flexible semiconductor films disposed on vapor-releasing adhesives'20169,455,180'Controlled spalling of fine features'20169,418,870'Silicon germanium-on-insulator formation by thermal mixing'20169,406,717'Passivation of back-illuminated image sensor'20169,397,246'Monolithic integration of heterojunction solar cells'20169,394,178'Wafer scale epitaxial graphene transfer'20169,368,420'Flexible, stretchable electronic devices'20169,368,407'Crack control for substrate separation'20169,368,415'Non-destructive, wafer scale method to evaluate defect density in heterogeneous epitaxial layers'20169,331,229'Heterojunction III-V solar cell performance'20169,324,566'Controlled spalling using a reactive material stack'20169,324,872'Back gate single-crystal flexible thin film transistor and method of making'20169,324,564'Spalling with laser-defined spall edge regions'20169,308,714'Method for improving surface quality of spalled substrates'20169,306,106'Monolithic integration of heterojunction solar cells'20169,293,476'Integrating active matrix inorganic light emitting diodes for display devices'20169,281,247'Strained silicon and strained silicon germanium on insulator field-effect transistor'20169,275,867'Method for improving quality of spalled material layers'20169,263,634'Thin light emitting diode and fabrication method'20169,245,747'Engineered base substrates for releasing III-V epitaxy through spalling'20169,246,032'III-V photovoltaic elements'20169,240,432'Passivation of back-illuminated image sensor'20169,236,271'Laser-initiated exfoliation of group III-nitride films and applications for layer transfer and patterning'20169,227,855'Large-scale electricity-less disinfection of fluent water'20169,224,755'Flexible active matrix display'20159,219,187'Solar-powered energy-autonomous silicon-on-insulator device'20159,205,631'Controlling the melt front of thin film applications'20159,209,216'Passivation of back-illuminated image sensor'20159,150,434'Electricity-less water disinfection'20159,136,402'High efficiency flexible solar cells for consumer electronics'20159,130,105'Thin light emitting diode and fabrication method'20159,105,518'Method of large-area circuit layout recognition'20159,099,596'Heterojunction photovoltaic device and fabrication method'20159,096,050'Wafer scale epitaxial graphene transfer'20159,079,269'Spalling with laser-defined spall edge regions'20159,064,743'Flexible, stretchable electronic devices'20159,064,722'Breakdown voltage multiplying integration scheme'20159,059,073'Method for controlled removal of a semiconductor device layer from a base substrate'20159,058,990'Controlled spalling of group III nitrides containing an embedded spall releasing plane'20159,048,365'Tunable light-emitting diode'20159,041,167'Radiation hardened SOI structure and method of making same'20159,040,432'Method for facilitating crack initiation during controlled substrate spalling'20159,040,392'Method for controlled removal of a semiconductor device layer from a base substrate'20159,018,675'Heterojunction III-V photovoltaic cell fabrication'20158,981,449'Extremely thin semiconductor on insulator (ETSOI) logic and memory hybrid chip'20158,969,109'Tunable light-emitting diode'20158,969,174'Fixed curvature force loading of mechanically spalled films'20158,969,992'Autonomous integrated circuits'20158,946,054'Crack control for substrate separation'20158,940,569'Dual-gate bio/chem sensor'20158,936,961'Removal of stressor layer from a spalled layer and method of making a bifacial solar cell using the same'20158,933,515'Device structure, layout and fabrication method for uniaxially strained transistors'20158,933,456'Germanium-containing release layer for transfer of a silicon layer to a substrate'20158,927,318'Spalling methods to form multi-junction photovoltaic structure'20158,927,431'High-rate chemical vapor etch of silicon substrates'20158,927,338'Flexible, stretchable electronic devices'20158,921,209'Defect free strained silicon on insulator (SSOI) substrates'20148,916,450'Method for improving quality of spalled material layers'20148,912,424'Multi-junction photovoltaic device and fabrication method'20148,912,020'Integrating active matrix inorganic light emitting diodes for display devices'20148,906,779'Solar-powered energy-autonomous silicon-on-insulator device'20148,901,713'Extremely thin semiconductor-on-insulator with back gate contact'20148,891,266'Monolithic high voltage multiplier having high voltage semiconductor diodes and high-k capacitors'20148,890,247'Extremely thin semiconductor-on-insulator with back gate contact'20148,871,620'III-V photovoltaic elements'20148,866,227'Thin semiconductor-on-insulator MOSFET with co-integrated silicon, silicon germanium and silicon doped with carbon channels'20148,865,530'Extremely thin semiconductor on insulator (ETSOI) logic and memory hybrid chip'20148,859,348'Strained silicon and strained silicon germanium on insulator'20148,860,005'Thin light emitting diode and fabrication method'20148,853,529'Flexible III-V solar cell structure'20148,841,203'Method for forming two device wafers from a single base substrate utilizing a controlled spalling process'20148,828,138'FET nanopore sensor'20148,823,127'Multijunction photovoltaic cell fabrication'20148,823,143'Electrodeposition method for forming Ge on semiconductor substrates'20148,809,164'Method of large-area circuit layout recognition'20148,809,168'Growing compressively strained silicon directly on silicon at low temperatures'20148,802,477'Heterojunction III-V photovoltaic cell fabrication'20148,765,577'Defect free strained silicon on insulator (SSOI) substrates'20148,753,528'Etchant for controlled etching of Ge and Ge-rich silicon germanium alloys'20148,748,296'Edge-exclusion spalling method for improving substrate reusability'20148,716,037'Measurement of CMOS device channel strain by X-ray diffraction'20148,709,957'Spalling utilizing stressor layer portions'20148,709,914'Method for controlled layer transfer'20148,703,521'Multijunction photovoltaic cell fabrication'20148,685,804'Enhancement of charge carrier mobility in transistors'20148,679,943'Fixed curvature force loading of mechanically spalled films'20148,664,058'Semiconductor device having silicon on stressed liner (SOL)'20148,659,083'Enhancement of charge carrier mobility in transistors'20148,658,444'Semiconductor active matrix on buried insulator'20148,659,110'Single-junction photovoltaic cell'20148,653,360'Compositionally-graded band gap heterojunction solar cell'20148,642,431'N-type carrier enhancement in semiconductors'20148,633,097'Single-junction photovoltaic cell'20148,624,104'Heterojunction III-V solar cell performance'20148,610,212'Semiconductor active matrix on buried insulator'20138,592,323'Method of large-area circuit layout recognition'20138,575,655'Method and structure for PMOS devices with high K metal gate integration and SiGe channel engineering'20138,569,803'BEOL compatible FET structrure'20138,569,097'Flexible III-V solar cell structure'20138,530,337'Method of large-area circuit layout recognition'20138,518,807'Radiation hardened SOI structure and method of making same'20138,486,776'Strained devices, methods of manufacture and design structures'20138,476,152'N-type carrier enhancement in semiconductors'20138,450,184'Thin substrate fabrication using stress-induced spalling'20138,440,547'Method and structure for PMOS devices with high K metal gate integration and SiGe channel engineering'20138,441,042'BEOL compatible FET structure'20138,415,253'Low-temperature in-situ removal of oxide from a silicon surface during CMOS epitaxial processing'20138,399,933'Semiconductor device having silicon on stressed liner (SOL)'20138,368,143'Strained thin body semiconductor-on-insulator substrate and device'20138,361,859'Stressed transistor with improved metastability'20138,361,889'Strained semiconductor-on-insulator by addition and removal of atoms in a semiconductor-on-insulator'20138,354,694'CMOS transistors with stressed high mobility channels'20138,343,863'N-type carrier enhancement in semiconductors'20138,298,923'Germanium-containing release layer for transfer of a silicon layer to a substrate'20128,288,218'Device structure, layout and fabrication method for uniaxially strained transistors'20128,247,261'Thin substrate fabrication using stress-induced substrate spalling'20128,227,792'Relaxed low-defect SGOI for strained SI CMOS applications'20128,178,430'N-type carrier enhancement in semiconductors'20128,169,025'Strained CMOS device, circuit and method of fabrication'20128,138,523'Semiconductor device having silicon on stressed liner (SOL)'20128,124,470'Strained thin body semiconductor-on-insulator substrate and device'20128,053,759'Ion implantation for suppression of defects in annealed SiGe layers'20118,039,371'Reduced defect semiconductor-on-insulator hetero-structures'20117,999,344'Optoelectronic device with germanium photodetector'20117,968,459'Ion implantation combined with in situ or ex situ heat treatment for improved field effect transistors'20117,935,612'Layer transfer using boron-doped SiGe layer'20117,897,444'Strained semiconductor-on-insulator (sSOI) by a simox method'20117,893,492'Nanowire mesh device and method of fabricating same'20117,892,945'Nanowire mesh device and method of fabricating same'20117,880,241'Low-temperature electrically activated gate electrode and method of fabricating same'20117,833,884'Strained semiconductor-on-insulator by Si:C combined with porous process'20107,816,664'Defect reduction by oxidation of silicon'20107,790,495'Optoelectronic device with germanium photodetector'20107,785,982'Structures containing electrodeposited germanium and methods for their fabrication'20107,723,791'Strained silicon directly-on-insulator substrate with hybrid crystalline orientation and different stress levels'20107,705,345'High performance strained silicon FinFETs device and method for forming same'20107,682,917'Disposable metallic or semiconductor gate spacer'20107,679,141'High-quality SGOI by annealing near the alloy melting point'20107,592,671'Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer'20097,550,370'Method of forming thin SGOI wafers with high relaxation and low stacking fault defect density'20097,511,317'Porous silicon for isolation region formation and related structure'20097,507,988'Semiconductor heterostructure including a substantially relaxed, low defect density SiGe layer'20097,501,318'Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal'20097,494,852'Method for creating a Ge-rich semiconductor material for high-performance CMOS circuits'20097,485,539'Strained semiconductor-on-insulator (sSOI) by a simox method'20097,473,587'High-quality SGOI by oxidation near the alloy melting temperature'20097,442,993'Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer'20087,423,303'Strained silicon directly-on-insulator substrate with hybrid crystalline orientation and different stress levels'20087,358,166'Relaxed, low-defect SGOI for strained Si CMOS applications'20087,348,253'High-quality SGOI by annealing near the alloy melting point'20087,342,293'Bipolar junction transistors (BJTS) with second shallow trench isolation (STI) regions, and methods for forming same'20087,304,328'Use of hydrogen implantation to improve material properties of silicon-germanium-on-insulator material made by thermal diffusion'20077,271,043'Method for manufacturing strained silicon directly-on-insulator substrate with hybrid crystalline orientation and different stress levels'20077,247,546'Method of forming strained silicon materials with improved thermal conductivity'20077,172,930'Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer'20077,169,226'Defect reduction by oxidation of silicon'20077,141,115'Method of producing silicon-germanium-on-insulator material using unstrained Ge-containing source layers'20067,125,458'Formation of a silicon germanium-on-insulator structure by oxidation of a buried porous silicon layer'20067,084,050'Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal'20067,074,686'Method of creating high-quality relaxed SiGe-on-insulator for strained Si CMOS applications'20067,067,400'Method for preventing sidewall consumption during oxidation of SGOI islands'20067,049,660'High-quality SGOI by oxidation near the alloy melting temperature'2006Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004–2021Patents assigned to IBM (301)· patent assignee history
2004–2021Based in Wappingers Falls, NY, US· patent location history
2011–2017Based in Yorktown Heights, NY, US· patent location history
2012–2019Patents assigned to BEDELL STEPHEN W (69)· patent assignee history
2012–2019Patents assigned to SADANA DEVENDRA K (46)· patent assignee history
2012–2019Patents assigned to FOGEL KEITH E (21)· patent assignee history
2012–2013Based in Armonk, NY, US· patent location history
2013–2019Patents assigned to SHAHRJERDI DAVOOD (27)· patent assignee history
2013–2016Based in Wappinger Falls, NY, US· patent location history
2019Based in Highland Falls, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 301 | 2004–2021 |
| BEDELL STEPHEN Wself | 69 | 2012–2019 |
| SADANA DEVENDRA K | 46 | 2012–2019 |
| SHAHRJERDI DAVOOD | 27 | 2013–2019 |
| FOGEL KEITH E | 21 | 2012–2019 |
Locations
| Location | Patents | Span |
|---|---|---|
| Wappingers Falls, New York, US | 293 | 2004–2021 |
| Yorktown Heights, New York, US | 14 | 2011–2017 |
| Wappinger Falls, New York, US | 4 | 2013–2016 |
| Armonk, New York, US | 2 | 2012–2013 |
| Highland Falls, New York, US | 1 | 2019 |