Inventor

C. Rinn Cleavelin

Inventor

Lubbock, TX, US

Overview

36→

Patents

1988–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 36 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices18%

H10BElectronic memory devices16%

G11CStatic stores12%

H01LSemiconductor devices8%

H10NElectric solid-state devices not otherwise provided for7%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h107%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests7%

H10KOrganic electric solid-state devices6%

G06TImage data processing or generation, in general4%

B82YSpecific uses or applications of nanostructures3%

PatentTitleYear

10,741,761Methods of making sealed resistive change elements2020 10,700,131Non-linear resistive change memory cells and arrays2020 10,403,683Methods for forming crosspoint arrays of resistive change memory cells2019 10,355,206Sealed resistive change elements2019 10,249,684Resistive change elements incorporating carbon based diode select devices2019 9,917,139'Resistive change element array using vertically oriented bit lines'2018 9,783,255'Cross point arrays of 1-R nonvolatile resistive change memory cells using continuous nanotube fabrics'2017 9,390,790'Carbon based nonvolatile cross point memory incorporating carbon based diode select devices and MOSFET select devices for memory and logic applications'2016 9,053,966'Integrated circuits with aligned (100) NMOS and (110) PMOS finFET sidewall channels'2015 8,941,094'Methods for adjusting the conductivity range of a nanotube fabric layer'2015 8,872,220'Integrated circuits with aligned (100) NMOS and (110) PMOS FinFET sidewall channels'2014 8,581,317'SOI MuGFETs having single gate electrode level'2013 8,410,519'Integrated circuits with aligned (100) NMOS and (110) PMOS FinFET sidewall channels'2013 8,138,035'Method for forming integrated circuits with aligned (100) NMOS and (110) PMOS FinFET sidewall channels'2012 8,067,792'Memory device with memory cell including MuGFET and FIN capacitor'2011 7,960,234'Multiple-gate MOSFET device and associated manufacturing methods'2011 7,939,393'Method of adjusting FDSOI threshold voltage through oxide charges generation in the buried oxide'2011 7,897,994'Method of making (100) NMOS and (110) PMOS sidewall surface on the same fin orientation for multiple gate MOSFET with DSB substrate'2011 7,793,186'System and method for increasing the extent of built-in self-testing of memory and circuitry'2010 7,752,518'System and method for increasing the extent of built-in self-testing of memory and circuitry'2010 7,683,417'Memory device with memory cell including MuGFET and fin capacitor'2010 7,638,843'Integrating high performance and low power multi-gate devices'2009 7,531,398'Methods and devices employing metal layers in gates to introduce channel strain'2009 7,189,627'Method to improve SRAM performance and stability'2007 7,122,442'Method and system for dopant containment'2006 6,483,938'System and method for classifying an anomaly'2002 6,292,582'Method and system for identifying defects in a semiconductor'2001 6,246,787'System and method for knowledgebase generation and management'2001 6,205,239'System and method for circuit repair'2001 6,097,296'Apparatus and method for detecting tornadoes'2000 6,054,684'Ultra fast temperature ramp up and down in a furnace using interleaving shutters'2000 5,696,835'Apparatus and method for aligning and measuring misregistration'1997 5,155,055'Method of making an electrically-erasable, electrically-programmable read-only memory cell with self-aligned tunnel'1992 5,008,721'Electrically-erasable, electrically-programmable read-only memory cell with self-aligned tunnel'1991 4,839,010'Forming an antireflective coating for VLSI metallization'1989 4,749,440'Gaseous process and apparatus for removing films from substrates'1988

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1988–2015Patents assigned to TEXAS INSTRUMENTS INC (25)· patent assignee history

1988–2020Based in Lubbock, TX, US· patent location history

2006–2015Based in Dallas, TX, US· patent location history

2011–2013Patents assigned to XIONG WEIZE (4)· patent assignee history

2011–2013Patents assigned to MARSHALL ANDREW (2)· patent assignee history

2012–2013Patents assigned to CLEAVELIN CLOVES RINN (3)· patent assignee history

2015–2020Patents assigned to NANTERO INC (9)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
TEXAS INSTRUMENTS INC	25	1988–2015
NANTERO INC	9	2015–2020
XIONG WEIZE	4	2011–2013
CLEAVELIN CLOVES RINNself	3	2012–2013
MARSHALL ANDREW	2	2011–2013

Locations

Location	Patents	Span
Lubbock, Texas, US	22	1988–2020
Dallas, Texas, US	14	2006–2015