Inventor

Axel Brintzinger

Inventor

Dresden, DE

Overview

41→

Patents

1999–2009

Patent span

Electricity

Primary field (CPC H)

Patents· 41 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1060%

H10DInorganic electric semiconductor devices15%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h109%

H05KPrinted circuits6%

Y10TTechnical subjects covered by former us classification3%

C23CCoating metallic material1%

C25DProcesses for the electrolytic or electrophoretic production of coatings1%

G01RMeasuring electric variables1%

G11CStatic stores1%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%

PatentTitleYear

7,514,798'Arrangement for the protection of three-dimensional structures on wafers'2009 7,393,782'Process for producing layer structures for signal distribution'2008 7,390,742'Method for producing a rewiring printed circuit board'2008 7,368,375'Electronic component with compliant elevations having electrical contact areas and method for producing it'2008 7,335,591'Method for forming three-dimensional structures on a substrate'2008 7,332,430'Method for improving the mechanical properties of BOC module arrangements'2008 7,271,095'Process for producing metallic interconnects and contact surfaces on electronic components'2007 7,235,859'Arrangement and process for protecting fuses/anti-fuses'2007 7,172,966'Method for fabricating metallic interconnects on electronic components'2007 7,169,647'Connection between a semiconductor chip and an external conductor structure and method for producing it'2007 7,115,496'Method for protecting the redistribution layer on wafers/chips'2006 7,087,975'Area efficient stacking of antifuses in semiconductor device'2006 6,943,101'Manufacturing of a corrosion protected interconnect on a substrate'2005 6,919,264'Method for the solder-stop structuring of elevations on wafers'2005 6,911,390'Fabrication method for an interconnect on a substrate'2005 6,888,215'Dual damascene anti-fuse with via before wire'2005 6,882,027'Methods and apparatus for providing an antifuse function'2005 6,866,943'Bond pad structure comprising tungsten or tungsten compound layer on top of metallization level'2005 6,720,212'Method of eliminating back-end rerouting in ball grid array packaging'2004 6,638,870'Forming a structure on a wafer'2003 6,566,238'Metal wire fuse structure with cavity'2003 6,509,208'Method for forming structures on a wafer'2003 6,495,918'Chip crack stop design for semiconductor chips'2002 6,495,901'Multi-level fuse structure'2002 6,486,526'Crack stop between neighboring fuses for protection from fuse blow damage'2002 6,465,282'Method of forming a self-aligned antifuse link'2002 6,458,631'Method for fabricating an integrated circuit, in particular an antifuse'2002 6,436,585'Method of using optical proximity effects to create electrically blown fuses with sub-critical dimension neck downs'2002 6,433,404'Electrical fuses for semiconductor devices'2002 6,323,535'Electrical fuses employing reverse biasing to enhance programming'2001 6,288,436'Mixed fuse technologies'2001 6,274,440'Manufacturing of cavity fuses on gate conductor level'2001 6,268,638'Metal wire fuse structure with cavity'2001 6,261,937'Method for forming a semiconductor fuse'2001 6,251,710'Method of making a dual damascene anti-fuse with via before wire'2001 6,252,292'Vertical electrical cavity-fuse'2001 6,242,789'Vertical fuse and method of fabrication'2001 6,218,279'Vertical fuse and method of fabrication'2001 6,210,995'Method for manufacturing fusible links in a semiconductor device'2001 6,060,398'Guard cell for etching'2000 6,008,523'Electrical fuses with tight pitches and method of fabrication in semiconductors'1999

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1999–2005Patents assigned to IBM (14)· patent assignee history

1999–2001Patents assigned to SIEMENS AG (3)· patent assignee history

1999–2005Based in Fishkill, NY, US· patent location history

2001–2002Patents assigned to INFINEON TECHNOLOGIES CORP (6)· patent assignee history

2001Patents assigned to IBM CORP (1)· patent assignee history

2002–2009Patents assigned to INFINEON TECHNOLOGIES AG (25)· patent assignee history

2002–2009Based in Dresden, DE· patent location history

2006Based in Livermore, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INFINEON TECHNOLOGIES AG	25	2002–2009
IBM	14	1999–2005
INFINEON TECHNOLOGIES CORP	6	2001–2002
SIEMENS AG	3	1999–2001
IBM CORP	1	2001

Locations

Location	Patents	Span
Dresden, DE	21	2002–2009
Fishkill, New York, US	19	1999–2005
Livermore, California, US	1	2006