Inventor
Joseph W. Cowan
Inventor
West Linn, OR, US
Overview
Patents· 8 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G01Rprimary
G01RMeasuring electric variables56%
G06FElectric digital data processing33%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1011%
PatentTitleYear
6,986,112'Method of mapping logic failures in an integrated circuit die'20066,951,000'Simulated voltage contrasted image generator and comparator'20056,864,563'Grounding mechanism for semiconductor devices'20056,865,435'Method of translating a net description of an integrated circuit die'20056,817,004'Net segment analyzer for chip CAD layout'20046,747,473'Device under interface card with on-board testing'20046,605,951'Interconnector and method of connecting probes to a die for functional analysis'20036,140,581'Grounded packaged semiconductor structure and manufacturing method therefor'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000Patents assigned to MITSUBISHI ELECTRONICS AMERICA (1)· patent assignee history
2000Based in Durham, NC, US· patent location history
2003–2006Patents assigned to LSI LOGIC CORP (7)· patent assignee history
2003–2006Based in West Linn, OR, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| LSI LOGIC CORP | 7 | 2003–2006 |
| MITSUBISHI ELECTRONICS AMERICA | 1 | 2000 |
Locations
| Location | Patents | Span |
|---|---|---|
| West Linn, OR, US | 7 | 2003–2006 |
| Durham, NC, US | 1 | 2000 |