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Inventor

Ralph D. Wittig

Inventor
Menlo Park, CA, US

Overview

50→
Patents
2000–2021
Patent span
Physics
Primary field (CPC G)

Patents· 50 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing53%
H03KPulse technique42%
G02BOptical elements, systems or apparatus2%
H01JElectric discharge tubes or discharge lamps2%
H04LTransmission of digital information, e.g. telegraphic communication2%
PatentTitleYear
10,990,552Streaming interconnect architecture for data processing engine array202110,866,753Data processing engine arrangement in a device202010,860,766Compilation flow for a heterogeneous multi-core architecture202010,824,434Dynamically structured single instruction, multiple data (SIMD) instructions202010,802,807Control and reconfiguration of data flow graphs on heterogeneous computing platform202010,747,690Device with data processing engine array20209,846,660Heterogeneous multiprocessor platform targeting programmable integrated circuits20179,218,443'Heterogeneous multiprocessor program compilation targeting programmable integrated circuits'20158,479,042'Transaction-level lockstep'20138,447,957'Coprocessor interface architecture and methods of operating the same'20138,443,230'Methods and systems with transaction-level lockstep'20138,352,659'Segmentation and reassembly of a data value communicated via interrupt transactions'20138,296,557'Providing multiple selectable configuration sources for programmable integrated circuits with fail safe mechanism'20127,948,269'System and method for open drain/open collector structures in an integrated circuit'20117,786,762'Generic buffer circuits and methods for out of band signaling'20107,721,090'Event-driven simulation of IP using third party event-driven simulators'20107,340,585'Method and system for fast linked processor in a system on a chip (SoC)'20087,310,594'Method and system for designing a multiprocessor'20077,248,073'Configurable logic element with expander structures'20077,243,330'Method and apparatus for providing self-implementing hardware-software libraries'20077,181,718'Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks'20077,145,360'Configurable logic element with expander structures'20067,111,273'Softpal implementation and mapping technology for FPGAs with dedicated resources'20066,946,874'Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks'20056,847,229'Configurable logic element with expander structures'20056,803,786'Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks'20046,630,841'Configurable logic element with expander structures'20036,603,332'Configurable logic block for PLD with logic gate for combining output with another configurable logic block'20036,583,645'Field programmable optical arrays'20036,505,337'Method for implementing large multiplexers with FPGA lookup tables'20036,501,296'Logic/memory circuit having a plurality of operating modes'20026,457,164'Hetergeneous method for determining module placement in FPGAs'20026,400,180'Configurable lookup table for programmable logic devices'20026,396,302'Configurable logic element with expander structures'20026,388,466'FPGA logic element with variable-length shift register capability'20026,353,920'Method for implementing wide gates and tristate buffers using FPGA carry logic'20026,292,925'Context-sensitive self implementing modules'20016,288,569'Memory array with hard and soft decoders'20016,259,205'High-pressure discharge lamp with a discharge vessel having conical of concentric ends'20016,260,182'Method for specifying routing in a logic module by direct module communication'20016,243,851'Heterogeneous method for determining module placement in FPGAs'20016,237,129'Method for constraining circuit element positions in structured layouts'20016,216,258'FPGA modules parameterized by expressions'20016,208,163'FPGA configurable logic block with multi-purpose logic/memory circuit'20016,191,610'Method for implementing large multiplexers with FPGA lookup tables'20016,184,712'FPGA configurable logic block with multi-purpose logic/memory circuit'20016,150,839'Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM'20006,150,838'FPGA configurable logic block with multi-purpose logic/memory circuit'20006,118,300'Method for implementing large multiplexers with FPGA lookup tables'20006,091,263'Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM'2000

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2000–2021Patents assigned to XILINX INC (49)· patent assignee history
2000–2021Based in Menlo Park, CA, US· patent location history
2000Based in Sunnyvale, CA, US· patent location history
2012–2013Patents assigned to WITTIG RALPH D (5)· patent assignee history
2012–2013Patents assigned to BALLANTYNE RICHARD S (2)· patent assignee history
2012–2013Patents assigned to PALUSZKIEWICZ MARK (2)· patent assignee history
2013Patents assigned to JAMES-ROXBY PHILIP B (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
XILINX INC492000–2021
WITTIG RALPH Dself52012–2013
BALLANTYNE RICHARD S22012–2013
JAMES-ROXBY PHILIP B22013
PALUSZKIEWICZ MARK22012–2013
Locations
LocationPatentsSpan
Menlo Park, California, US482000–2021
Sunnyvale, California, US22000