Inventor
Chang-Jen Hsieh
Inventor
Hsinchu, TW
Overview
Patents· 5 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Bprimary
H10BElectronic memory devices56%
H10DInorganic electric semiconductor devices22%
H01LSemiconductor devices11%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%
PatentTitleYear
8,809,179'Method for reducing topography of non-volatile memory and resulting memory cells'20147,951,670'Flash memory cell with split gate structure and method for forming the same'20117,667,261'Split-gate memory cells and fabrication methods thereof'20107,652,318'Split-gate memory cells and fabrication methods thereof'20107,226,828'Architecture to monitor isolation integrity between floating gate and source line'2007Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2007–2014Patents assigned to TAIWAN SEMICONDUCTOR MFG (5)· patent assignee history
2007–2014Based in Hsinchu, TW· patent location history
2014Patents assigned to CHU YI-SHIN (1)· patent assignee history
2014Patents assigned to HSIEH CHANG-JEN (1)· patent assignee history
2014Patents assigned to HUANG CHEN-MING (1)· patent assignee history
2014Patents assigned to LIN DEREK (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG | 5 | 2007–2014 |
| CHU YI-SHIN | 1 | 2014 |
| HSIEH CHANG-JENself | 1 | 2014 |
| HUANG CHEN-MING | 1 | 2014 |
| LIN DEREK | 1 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu, TW | 5 | 2007–2014 |