Inventor
Peter B. Gray
Inventor
Jericho, VT, US
Overview
Patents· 26 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices62%
H01LSemiconductor devices12%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests7%
PatentTitleYear
10,367,083Compact device structures for a bipolar junction transistor20199,318,584'Isolation scheme for bipolar transistors in BiCMOS technology'20169,231,087'Bipolar junction transistors with self-aligned terminals'20169,059,196'Bipolar junction transistors with self-aligned terminals'20158,921,195'Isolation scheme for bipolar transistors in BiCMOS technology'20148,810,005'Bipolar device having a monocrystalline semiconductor intrinsic base to extrinsic base link-up region'20148,716,837'Bipolar junction transistors with a link region connecting the intrinsic and extrinsic bases'20148,710,500'Bipolar junction transistor with a self-aligned emitter and base'20148,536,012'Bipolar junction transistors with a link region connecting the intrinsic and extrinsic bases'20138,513,706'Heterojunction bipolar transistors with reduced base resistance'20138,492,237'Methods of fabricating a bipolar junction transistor with a self-aligned emitter and base'20138,482,101'Bipolar transistor structure and method including emitter-base interface impurity'20138,405,186'Transistor structure with a sidewall-defined intrinsic base to extrinsic base link-up region and method of forming the structure'20138,389,372'Heterojunction bipolar transistors with reduced base resistance'20137,972,919'Vertical PNP transistor and method of making same'20117,709,338'BiCMOS devices with a self-aligned emitter and methods of fabricating such BiCMOS devices'20107,491,985'Method of collector formation in BiCMOS technology'20097,265,010'High performance vertical PNP transistor method'20077,217,628'High performance integrated vertical transistors and method of making the same'20077,214,593'Passivation for improved bipolar yield'20077,002,190'Method of collector formation in BiCMOS technology'20066,909,164'High performance vertical PNP transistor and method'20056,670,255'Method of fabricating lateral diodes and bipolar transistors'20036,597,050'Method of contacting a silicide-based schottky diode and diode so formed'20036,448,124'Method for epitaxial bipolar BiCMOS'20026,121,122'Method of contacting a silicide-based schottky diode'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2015Patents assigned to IBM (23)· patent assignee history
2000–2011Based in Essex Junction, VT, US· patent location history
2003–2007Based in Essex, VT, US· patent location history
2013Patents assigned to GRAY PETER B (5)· patent assignee history
2013Patents assigned to HARAME DAVID L (3)· patent assignee history
2013Patents assigned to LIU QIZHI (3)· patent assignee history
2013–2019Based in Jericho, VT, US· patent location history
2016–2019Patents assigned to GLOBALFOUNDRIES INC (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 23 | 2000–2015 |
| GRAY PETER Bself | 5 | 2013 |
| GLOBALFOUNDRIES INC | 3 | 2016–2019 |
| HARAME DAVID L | 3 | 2013 |
| LIU QIZHI | 3 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Jericho, VT, US | 14 | 2013–2019 |
| Essex Junction, VT, US | 10 | 2000–2011 |
| Essex, VT, US | 2 | 2003–2007 |