Inventor
Jeffrey C. Shearer
Inventor
Albany, NY, US
Overview
Patents· 27 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices31%
H10DInorganic electric semiconductor devices31%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1020%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1015%
H10BElectronic memory devices2%
Y02PClimate change mitigation technologies in the production or processing of goods1%
PatentTitleYear
11,024,715FinFET gate cut after dummy gate removal202110,804,148Buried contact to provide reduced VFET feature-to-feature tolerance requirements202010,796,957Buried contact to provide reduced VFET feature-to-feature tolerance requirements202010,629,698Method and structure for enabling high aspect ratio sacrificial gates202010,600,868FinFET gate cut after dummy gate removal202010,586,733Multi-level air gap formation in dual-damascene structure202010,446,452Method and structure for enabling controlled spacer RIE201910,396,181Forming stacked nanowire semiconductor device201910,304,692Method of forming field effect transistor (FET) circuits, and forming integrated circuit (IC) chips with the FET circuits201910,256,326Forming stacked nanowire semiconductor device201910,249,533Method and structure for forming a replacement contact201910,249,753Gate cut on a vertical field effect transistor with a defined-width inorganic mask201910,229,854FinFET gate cut after dummy gate removal201910,224,239Multi-level air gap formation in dual-damascene structure201910,204,827Multi-level air gap formation in dual-damascene structure201910,074,730Forming stacked nanowire semiconductor device20189,882,048'Gate cut on a vertical field effect transistor with a defined-width inorganic mask'20189,859,212'Multi-level air gap formation in dual-damascene structure'20189,842,739'Method and structure for enabling high aspect ratio sacrificial gates'20179,754,942'Single spacer for complementary metal oxide semiconductor process flow'20179,748,146'Single spacer for complementary metal oxide semiconductor process flow'20179,716,184'Enabling large feature alignment marks with sidewall image transfer patterning'20179,659,779'Method and structure for enabling high aspect ratio sacrificial gates'20179,627,277'Method and structure for enabling controlled spacer RIE'20179,536,744'Enabling large feature alignment marks with sidewall image transfer patterning'20179,450,095'Single spacer for complementary metal oxide semiconductor process flow'20169,318,574'Method and structure for enabling high aspect ratio sacrificial gates'2016Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2016–2020Patents assigned to IBM (25)· patent assignee history
2016–2021Based in Albany, NY, US· patent location history
2020–2021Patents assigned to TESSERA INC (2)· patent assignee history
2020Based in Slingerlands, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 25 | 2016–2020 |
| TESSERA INC | 2 | 2020–2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| Albany, New York, US | 25 | 2016–2021 |
| Slingerlands, New York, US | 2 | 2020 |