Inventor
Jiann-Jeng Duh
Inventor
San Jose, CA, US
Overview
Patents· 8 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing64%
G11CStatic stores36%
PatentTitleYear
7,710,789'Synchronous address and data multiplexed mode for SRAM'20107,246,300'Sequential flow-control and FIFO memory devices having error detection and correction capability with diagnostic bit generation'20077,209,983'Sequential flow-control and FIFO memory devices that are depth expandable in standard mode operation'20077,158,440'FIFO memory devices having write and read control circuits that support x4N, x2N and xN data widths during DDR and SDR modes of operation'20077,093,047'Integrated circuit memory devices having clock signal arbitration circuits therein and methods of performing clock signal arbitration'20067,076,610'FIFO memory devices having multi-port cache memory arrays therein that support hidden EDC latency and bus matching and methods of operating same'20066,795,360'Fifo memory devices that support all four combinations of DDR or SDR write modes with DDR or SDR read modes'20046,778,454'FIFO memory devices that support all combinations of DDR and SDR read and write modes'2004Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004–2010Patents assigned to INTEGRATED DEVICE TECH (8)· patent assignee history
2004–2010Based in San Jose, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEGRATED DEVICE TECH | 8 | 2004–2010 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 8 | 2004–2010 |