Inventor
Jiann-Tyng Tzeng
Inventor
Hsinchu, TW
Overview
Patents· 89 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices26%
H01LSemiconductor devices24%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1020%
G06FElectric digital data processing11%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices3%
H03KPulse technique2%
H10BElectronic memory devices2%
G02BOptical elements, systems or apparatus2%
G01RMeasuring electric variables1%
PatentTitleYear
11,133,255Metal patterning for internal cell routing202111,133,254Hybrid power rail structure202111,126,775IC layout, method, device, and system202111,121,256Semiconductor device integrating backside power grid and related integrated circuit and fabrication method202111,100,273Integrated circuit and method of manufacturing same202111,088,092Via rail solution for high power electromigration202111,080,454Integrated circuit, system, and method of forming the same202111,063,005Via rail solution for high power electromigration202111,055,469Power structure with power pick-up cell connecting to buried power rail202111,048,848Semiconductor device including region having both continuous regions, and method and system for generating layout diagram of same202111,043,426Dummy MOL removal for performance enhancement202111,024,580Random cut patterning202111,024,579Dual power structure with connection pins202111,018,157Local interconnect structure202110,977,417Semiconductor structure, device, and method202110,977,421System for and method of manufacturing an integrated circuit202110,971,493Integrated circuit device with high mobility and system of forming the integrated circuit202110,964,684Multiple fin height integrated circuit202110,950,456High-density semiconductor device202110,878,162Metal with buried power for increased IC device density202010,879,120Self aligned via and method for fabricating the same202010,878,161Method and structure to reduce cell width in integrated circuits202010,879,173Middle-end-of-line strap for standard cell202010,878,158Semiconductor device including cell region having more similar cell densities in different height rows, and method and system for generating layout diagram of same202010,879,229Integrated circuit, system for and method of forming an integrated circuit202010,867,102Inverted pitch IC structure, layout method, and system202010,867,833Buried metal for FinFET device and method202010,868,008Double rule integrated circuit layouts for a dual transmission gate202010,867,115System and method for calculating cell edge leakage202010,867,917Semiconductor device, associated method and layout202010,861,790Power strap structure for high performance and low current density202010,847,460Advanced metal connection with metal cut202010,833,061Semiconductor device including source/drain contact having height below gate stack202010,804,402Metal rail conductors for non-planar semiconductor devices202010,797,078Hybrid fin field-effect transistor cell structures and related methods202010,784,168Dummy MOL removal for performance enhancement202010,784,869Integrated circuit and method of manufacturing the same202010,769,342Pin access hybrid cell height design202010,763,365Metal rail conductors for non-planar semiconductor devices202010,734,377Integrated circuit, system for and method of forming an integrated circuit202010,714,485Semiconductor device which includes Fins202010,700,207Semiconductor device integrating backside power grid and related integrated circuit and fabrication method202010,658,292Metal patterning for internal cell routing202010,565,348System for and method of fabricating an integrated circuit202010,522,542Double rule integrated circuit layouts for a dual transmission gate201910,516,047Structure and formation method of semiconductor device structure201910,510,688Via rail solution for high power electromigration201910,510,776Semiconductor device with common active area and method for manufacturing the same201910,503,863Integrated circuit and method of manufacturing same201910,468,349Advanced metal connection with metal cut201910,467,374System and method for calculating cell edge leakage201910,446,406High-density semiconductor device201910,366,200System for and method of manufacturing a layout design of an integrated circuit201910,297,588Semiconductor device and fabrication method of the same201910,276,499Dual power structure with connection pins201910,204,857Middle end-of-line strap for standard cell201910,177,133Semiconductor device including source/drain contact having height below gate stack201910,170,422Power strap structure for high performance and low current density201910,162,930Method of adjusting metal line pitch201810,157,922Interconnect metal layout for integrated circuit201810,109,582Advanced metal connection with metal cut201810,096,522Dummy MOL removal for performance enhancement201810,074,657Method of manufacturing fins and semiconductor device which includes fins201810,050,028Semiconductor device with reduced leakage current201810,032,759High-density semiconductor device20189,984,964Integrated circuit having slot via and method of forming the same20189,911,697'Power strap structure for high performance and low current density'20189,837,353Middle end-of-line strap for standard cell20179,793,211'Dual power structure with connection pins'20179,741,654'Integrated circuit having slot via and method of forming the same'20179,679,994'High fin cut fabrication process'20179,659,115'Thermal analysis for tiered semiconductor structure'20179,478,492'Integrated circuit having slot via and method of forming the same'20169,442,510'Clock circuit and method of operating the same'20169,385,213'Integrated circuits and manufacturing methods thereof'20169,184,250'Semiconductor arrangement and formation thereof'20158,698,205'Integrated circuit layout having mixed track standard cell'20148,443,306'Planar compatible FDSOI design architecture'20138,362,573'Integrated circuits and manufacturing methods thereof'20138,122,406'Generating models for integrated circuits with sensitivity-based minimum change to existing models'20127,605,413'High voltage devices'20097,151,296'High voltage lateral diffused MOSFET device'20067,095,544'Micromirror and products using the same'20066,998,304'Method for integrated manufacturing of split gate flash memory with high voltage MOSFETS'20066,958,249'Method to monitor process charging effect'20056,947,196'Trench-embedded mirror structure for double substrate spatial light modulator'20056,929,969'Reflective spatial light modulator mirror device manufacturing process and layout method'20056,841,081'Method for manufacturing reflective spatial light modulator mirror devices'20056,660,624'Method for reducing fluorine induced defects on a bonding pad surface'2003Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2003–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG (15)· patent assignee history
2003–2005Based in Yilan County, TW· patent location history
2005–2021Based in Hsinchu, TW· patent location history
2005–2021Based in Hsin Chu, TW· patent location history
2006Based in Shiang Ilan, TW· patent location history
2012–2014Patents assigned to TZENG JIANN-TYNG (4)· patent assignee history
2012–2013Patents assigned to SCOTT DAVID B (2)· patent assignee history
2013Patents assigned to GUO TA-PEN (2)· patent assignee history
2016–2021Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (74)· patent assignee history
2020Based in Tu-Chun, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 74 | 2016–2021 |
| TAIWAN SEMICONDUCTOR MFG | 15 | 2003–2020 |
| TZENG JIANN-TYNGself | 4 | 2012–2014 |
| GUO TA-PEN | 2 | 2013 |
| SCOTT DAVID B | 2 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu, TW | 62 | 2005–2021 |
| Hsin Chu, TW | 22 | 2005–2021 |
| Yilan County, TW | 2 | 2003–2005 |
| Tu-Chun, TW | 1 | 2020 |
| Shiang Ilan, TW | 1 | 2006 |