Inventor
TZU-YING LIN
Inventor
TW
Overview
Patents· 27 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing19%
H10DInorganic electric semiconductor devices19%
H03KPulse technique17%
H01LSemiconductor devices15%
G01RMeasuring electric variables9%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%
G11CStatic stores4%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use4%
A42BHats1%
A62BDevices, apparatus or methods for life-saving1%
PatentTitleYear
12,593,497Integrated circuit in hybrid row height structure202612,557,393Method of semiconductor layout with different row heights202612,407,337Flip-flop circuit and method202512,401,348Footprint for multi-bit flip flop202512,395,157Footprint for multi-bit flip flop202512,369,389Integrated circuit in hybrid row height structure202512,353,816Structure and method of rectangular cell in semiconductor device202512,346,285Diagonal torus network202512,218,670Flip-flops having strong transistors and weak transistors202512,179,044Positive-pressure protective wear202412,166,487Bi-directional scan flip-flop circuit and method202412,107,581Clock gating circuit and method of operating the same202412,074,069Semiconductor device and integrated circuit in hybrid row height structure202412,066,489Scan flip-flops with pre-setting combinational logic202412,047,079Flip-flop circuit and method202412,040,800Low hold multi-bit flip-flop202412,039,242Structure and method of non-rectangular cell in semiconductor device202412,009,824Clock gating circuit and method of operating the same202411,943,939Integrated circuit device and method202411,791,213Integrated circuit in hybrid row height structure202311,682,665Semiconductor layout with different row heights202311,632,102Low-power flip-flop architecture with high-speed transmission gates202311,556,688Integrated circuit layout method and system202311,558,040Low hold multi-bit flip-flop202311,545,965Clock gating circuit and method of operating the same202311,509,293Footprint for multi-bit flip flop202211,355,395Integrated circuit in hybrid row height structure2022Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2022–2026Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (26)· patent assignee history
2022–2026Based in TW· patent location history
2023Patents assigned to TAIWAN SEMICONDUCTOR MFG CAMPUS LTD (1)· patent assignee history
2024Patents assigned to LIN CHAO TING (1)· patent assignee history
2024Patents assigned to LIN TZU YING (1)· patent assignee history
2024Patents assigned to LIN YUNG CHI (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 26 | 2022–2026 |
| LIN CHAO TING | 1 | 2024 |
| LIN TZU YINGself | 1 | 2024 |
| LIN YUNG CHI | 1 | 2024 |
| TAIWAN SEMICONDUCTOR MFG CAMPUS LTD | 1 | 2023 |
Locations
| Location | Patents | Span |
|---|---|---|
| TW | 27 | 2022–2026 |