Inventor
Chang-Pin Huang
Inventor
Yangmei Taoyuan, TW
Overview
Patents· 27 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1047%
H01LSemiconductor devices41%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%
A61BDiagnosis2%
F16JPistons2%
H04BTransmission2%
H10DInorganic electric semiconductor devices2%
PatentTitleYear
10,879,198Package with solder regions aligned to recesses202010,854,564Semiconductor device and manufacturing method thereof202010,825,804Hollow metal pillar packaging scheme202010,354,986Hollow metal pillar packaging scheme201910,269,737Method for manufacturing semiconductor structure201910,262,958Package with solder regions aligned to recesses201910,163,828Semiconductor device and fabricating method thereof201810,062,654Semicondcutor structure and semiconductor manufacturing process thereof201810,032,737Semiconductor device and manufacturing method thereof20189,947,630Package with solder regions aligned to recesses20189,943,239Optical sensing system and associated electronic device20189,852,985Conductive terminal on integrated circuit20179,812,434'Hollow metal pillar packaging scheme'20179,799,615'Package structures having height-adjusted molding members and methods of forming the same'20179,786,618'Semiconductor structure and manufacturing method thereof'20179,748,212'Shadow pad for post-passivation interconnect structures'20179,679,883'Hollow metal pillar packaging scheme'20179,640,498'Integrated fan-out (InFO) package structures and methods of forming same'20179,627,332'Integrated circuit structure and seal ring structure'20179,559,044'Package with solder regions aligned to recesses'20179,484,318'Semiconductor device and manufacturing method thereof'20169,461,106'MIM capacitor and method forming the same'20169,343,417'Hollow metal pillar packaging scheme'20169,318,456'Self-alignment structure for wafer level chip scale package'20169,048,149'Self-alignment structure for wafer level chip scale package'20158,963,328'Reducing delamination between an underfill and a buffer layer in a bond structure'20158,610,267'Reducing delamination between an underfill and a buffer layer in a bond structure'2013Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2013–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (3)· patent assignee history
2013Patents assigned to CHEN HSIEN-WEI (1)· patent assignee history
2013Patents assigned to CHEN YING-JU (1)· patent assignee history
2013Patents assigned to HUANG CHANG-PIN (1)· patent assignee history
2013–2020Based in Yangmei Taoyuan, TW· patent location history
2015–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (24)· patent assignee history
2016–2020Based in Taoyuan County, TW· patent location history
2016–2019Based in Taoyuan, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 24 | 2015–2020 |
| TAIWAN SEMICONDUCTOR MFG | 3 | 2013–2016 |
| CHEN HSIEN-WEI | 1 | 2013 |
| CHEN YING-JU | 1 | 2013 |
| HUANG CHANG-PINself | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Yangmei Taoyuan, TW | 15 | 2013–2020 |
| Taoyuan County, TW | 7 | 2016–2020 |
| Taoyuan, TW | 5 | 2016–2019 |