Inventor

John A. Fifield

Inventor

Underhill, VT, US

Overview

1984–2021

Patent span

Physics

Primary field (CPC G)

Patents· 176 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary

G11CStatic stores34%

H03KPulse technique15%

G06FElectric digital data processing10%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h108%

H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems6%

H10DInorganic electric semiconductor devices4%

G01RMeasuring electric variables3%

G05FSystems for regulating electric or magnetic variables3%

H05KPrinted circuits2%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%

PatentTitleYear

10,971,996Charge pump circuit with internal pre-charge configuration2021 10,826,489Selection circuit2020 10,707,845Ultra-low voltage level shifter2020 10,699,771Voltage boost circuit2020 10,673,321Charge pump circuit with built-in-retry2020 10,615,797High speed level translator2020 10,535,379Latching current sensing amplifier for memory array2020 10,446,239Memory array including distributed reference cells for current sensing2019 10,438,652Voltage boost circuit2019 10,429,434On-chip reliability monitor and method2019 10,395,752Margin test for multiple-time programmable memory (MTPM) with split wordlines2019 10,382,049On-chip calibration circuit and method with half-step resolution2019 10,255,987Margin test for one-time programmable memory (OTPM) array with common mode current source2019 10,224,932High speed level translator2019 10,224,710Electrostatic discharge power clamp with fail-safe design2019 10,192,590Differential voltage generator2019 10,186,860Electrostatic discharge device with fail-safe design2019 10,163,526Circuit and method for detecting time dependent dielectric breakdown (TDDB) shorts and signal-margin testing2018 10,127,970Voltage boost circuit2018 10,026,494Word line voltage generator for calculating optimum word line voltage level for programmable memory array2018 10,020,047Static random access memory (SRAM) write assist circuit with improved boost2018 9,953,727Circuit and method for detecting time dependent dielectric breakdown (TDDB) shorts and signal-margin testing2018 9,882,376'Electrostatic discharge power clamp with fail-safe design'2018 9,871,523'High speed level translator'2018 9,837,168Word line voltage generator for programmable memory array2017 9,779,783'Latching current sensing amplifier for memory array'2017 9,654,086'Operational amplifier with current-controlled up or down hysteresis'2017 9,646,125'Method for conversion of commercial microprocessor to radiation-hardened processor and resulting processor'2017 9,634,557'Voltage boost circuit'2017 9,508,420'Voltage-aware adaptive static random access memory (SRAM) write assist circuit'2016 9,503,090'High speed level translator'2016 9,093,175'Signal margin centering for single-ended eDRAM sense amplifier'2015 9,093,165'Distributed current clock for nano-magnetic element array'2015 9,042,551'Electronically programmable fuse security encryption'2015 9,000,837'Adjustable reference voltage generator for single-ended DRAM sensing devices'2015 8,990,478'Protection of one-time programmable (OTP) memory'2015 8,902,679'Memory array with on and off-state wordline voltages having different temperature coefficients'2014 8,773,920'Reference generator with programmable M and B parameters and methods of use'2014 8,724,365'Programmable semiconductor device'2014 8,649,239'Multi-bank random access memory structure with global and local signal buffering for improved performance'2014 8,562,210'Thermal sensor for semiconductor circuits'2013 8,300,489'Charge pump system and method utilizing adjustable output charge and compilation system and method for use by the charge pump'2012 8,228,713'SRAM having wordline up-level voltage adjustable to assist bitcell stability and design structure for same'2012 8,189,419'Apparatus for nonvolatile multi-programmable electronic fuse system'2012 8,184,465'Programmable semiconductor device'2012 8,035,452'Structure for transforming an input voltage to obtain linearity between input and output functions and system and method thereof'2011 8,028,195'Structure for indicating status of an on-chip power supply system'2011 8,027,207'Leakage compensated reference voltage generation system'2011 7,981,731'Method of forming a high impedance antifuse'2011 7,917,806'System and method for indicating status of an on-chip power supply system'2011 7,911,820'Regulating electrical fuse programming current'2011 7,904,658'Structure for power-efficient cache memory'2011 7,894,291'Circuit and method for controlling a standby voltage level of a memory'2011 7,872,897'Programmable semiconductor device'2011 7,873,921'Structure for a voltage detection circuit in an integrated circuit and method of generating a trigger flag signal'2011 7,847,605'Voltage detection circuit in an integrated circuit and method of generating a trigger flag signal'2010 7,825,469'Threshold voltage compensation for pixel design of CMOS image sensors'2010 7,772,918'Regulated voltage boost charge pump for an integrated circuit device'2010 7,737,766'Two stage voltage boost circuit, IC and design structure'2010 7,733,161'Voltage boost system, IC and design structure'2010 7,716,619'Design structure for implementing dynamic data path with interlocked keeper and restore devices'2010 7,710,195'Two stage voltage boost circuit with precharge circuit preventing leakage, IC and design structure'2010 7,688,654'Structure for differential eFUSE sensing without reference fuses'2010 7,687,883'Electronically programmable antifuse and circuits made therewith'2010 7,675,789'Programmable heavy-ion sensing device for accelerated DRAM soft error detection'2010 7,642,813'Error correcting logic system'2010 7,573,300'Current control mechanism for dynamic logic keeper circuits in an integrated circuit and method of regulating same'2009 7,551,470'Non volatile memory RAD-hard (NVM-rh) system'2009 7,550,789'Using electrically programmable fuses to hide architecture, prevent reverse engineering, and make a device inoperable'2009 7,541,834'System and the methods of managing a set of programmable fuses on an integrated circuit'2009 7,498,869'Voltage reference circuit for low voltage applications in an integrated circuit'2009 7,499,308'Programmable heavy-ion sensing device for accelerated DRAM soft error detection'2009 7,495,950'Voltage controlled static random access memory'2009 7,486,586'Voltage controlled static random access memory'2009 7,477,555'System and method for differential eFUSE sensing without reference fuses'2009 7,471,115'Error correcting logic system'2008 7,471,114'Design structure for a current control mechanism for power networks and dynamic logic keeper circuits'2008 7,466,171'Voltage detection circuit and circuit for generating a trigger flag signal'2008 7,466,188'Stress control mechanism for use in high-voltage applications in an integrated circuit'2008 7,466,582'Voltage controlled static random access memory'2008 7,442,583'Using electrically programmable fuses to hide architecture, prevent reverse engineering, and make a device inoperable'2008 7,352,609'Voltage controlled static random access memory'2008 7,336,095'Changing chip function based on fuse states'2008 7,336,102'Error correcting logic system'2008 7,307,457'Apparatus for implementing dynamic data path with interlocked keeper and restore devices'2007 7,305,515'Performance optimizing compiler for building a compiled DRAM'2007 7,276,775'Intrinsic dual gate oxide MOSFET using a damascene gate process'2007 7,268,577'Changing chip function based on fuse states'2007 7,262,987'SRAM cell using tunnel current loading devices'2007 7,227,239'Resettable fuse device and method of fabricating the same'2007 7,215,002'Electronically programmable antifuse and circuits made therewith'2007 7,167,053'Integrated circuit amplifier device and method using FET tunneling gate current'2007 7,098,083'High impedance antifuse'2006 7,085,971'ECC based system and method for repairing failed memory elements'2006 7,068,105'Low-voltage differential amplifier'2006 7,061,304'Fuse latch with compensated programmable resistive trip point'2006 7,061,308'Voltage divider for integrated circuits'2006 7,057,180'Detector for alpha particle or cosmic ray'2006 6,989,685'Method and system for maintaining uniform module junction temperature during burn-in'2006 6,982,591'Method and circuit for compensating for tunneling current'2006 6,975,169'Low-voltage differential amplifier'2005 6,956,417'Leakage compensation circuit'2005 6,944,090'Method and circuit for precise timing of signals in an embedded DRAM array'2005 6,917,319'Digital to analog converter using tunneling current element'2005 6,912,665'Automatic timing analyzer'2005 6,879,638'Method and apparatus for providing communication between electronic devices'2005 6,794,901'Apparatus for reducing soft errors in dynamic circuits'2004 6,753,590'High impedance antifuse'2004 6,737,907'Programmable DC voltage generator system'2004 6,711,078'Writeback and refresh circuitry for direct sensed DRAM macro'2004 6,697,293'Localized direct sense architecture'2004 6,667,633'Multiple finger off chip driver (OCD) with single level translator'2003 6,631,503'Temperature programmable timing delay system'2003 6,621,324'Redundant antifuse segments for improved programming efficiency'2003 6,577,154'Constant impedance driver for high speed interface'2003 6,577,156'Method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox'2003 6,570,806'System and method for improving DRAM single cell fail fixability and flexibility repair at module level and universal laser fuse/anti-fuse latch therefor'2003 6,552,944'Single bitline direct sensing architecture for high speed memory device'2003 6,538,932'Timing circuit and method for a compilable DRAM'2003 6,531,410'Intrinsic dual gate oxide MOSFET using a damascene gate process'2003 6,522,154'Oxide tracking voltage reference'2003 6,518,827'Sense amplifier threshold compensation'2003 6,496,037'Automatic off-chip driver adjustment based on load characteristics'2002 6,455,778'Micro-flex technology in semiconductor packages'2002 6,452,855'DRAM array interchangeable between single-cell and twin-cell array operation'2002 6,452,439'Inductive voltage spike generator with diode shunt'2002 6,444,490'Micro-flex technology in semiconductor packages'2002 6,445,611'Method and arrangement for preconditioning in a destructive read memory'2002 6,438,051'Stabilized direct sensing memory architecture'2002 6,420,925'Programmable latch device with integrated programmable element'2002 6,400,202'Programmable delay element and synchronous DRAM using the same'2002 6,384,666'Antifuse latch device with controlled current programming and variable trip point'2002 6,373,771'Integrated fuse latch and shift register for efficient programming and fuse readout'2002 6,348,827'Programmable delay element and synchronous DRAM using the same'2002 6,346,846'Methods and apparatus for blowing and sensing antifuses'2002 6,339,559'Decode scheme for programming antifuses arranged in banks'2002 6,300,687'Micro-flex technology in semiconductor packages'2001 6,285,229'Digital delay line with low insertion delay'2001 6,281,731'Control of hysteresis characteristic within a CMOS differential receiver'2001 6,272,054'Twin-cell memory architecture with shielded bitlines for embedded memory applications'2001 6,268,748'Module with low leakage driver circuits and method of operation'2001 6,243,283'Impedance control using fuses'2001 6,195,027'Capacitive precharging and discharging network for converting N bit input into M bit output'2001 6,177,817'Compensated-current mirror off-chip driver'2001 6,177,809'Redundant input/output driver circuit'2001 6,177,807'High frequency valid data strobe'2001 6,166,561'Method and apparatus for protecting off chip driver circuitry employing a split rail power supply'2000 6,141,245'Impedance control using fuses'2000 6,127,866'Delay-locked-loop (DLL) having symmetrical rising and falling clock edge type delays'2000 6,118,318'Self biased differential amplifier with hysteresis'2000 5,909,400'Three device BICMOS gain cell'1999 5,880,988'Reference potential for sensing data in electronic storage element'1999 5,873,053'On-chip thermometry for control of chip operating temperature'1999 5,796,270'Self-timed driver circuit'1998 5,761,114'Multi-level storage gain cell with stepline'1998 5,757,693'Gain memory cell with diode'1998 5,682,394'Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature'1997 5,675,774'Circuit element on a single ended interconnection for generating a logical output finish/clock signal when detecting a state change to logical \"1 or 0\".'1997 5,638,385'Fast check bit write for a semiconductor memory'1997 5,633,605'Dynamic bus with singular central precharge'1997 5,604,755'Memory system reset circuit'1997 5,581,567'Dual level error detection and correction employing data subsets from previously corrected data'1996 5,561,694'Self-timed driver circuit'1996 5,550,488'Self timed driver'1996 5,535,226'On-chip ECC status'1996 5,532,622'Multi-input transition detector with a single delay'1996 5,533,036'Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature'1996 5,307,356'Interlocked on-chip ECC system'1994 5,260,952'Fault tolerant logic system'1993 5,228,046'Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature'1993 5,134,616'Dynamic RAM with on-chip ECC and optimized bit and word redundancy'1992 5,058,115'Fault tolerant computer memory systems and components employing dual level error correction and detection with lock-up feature'1991 5,031,151'Wordline drive inhibit circuit implementing worldline redundancy without an access time penalty'1991 5,022,006'Semiconductor memory having bit lines with isolation circuits connected between redundant and normal memory cells'1991 5,010,524'Crosstalk-shielded-bit-line dram'1991 4,459,609'Charge-stabilized memory'1984

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1984–2020Patents assigned to IBM (158)· patent assignee history

1984–1991Based in Jericho, VT, US· patent location history

1991–2021Based in Underhill, VT, US· patent location history

2002Based in Chittenden County, VT, US· patent location history

2011–2012Based in Essex Junction, VT, US· patent location history

2012–2015Patents assigned to FIFIELD JOHN A (11)· patent assignee history

2016–2020Patents assigned to GLOBALFOUNDRIES INC (16)· patent assignee history

2016–2020Based in Burlington, VT, US· patent location history

2020–2021Patents assigned to MARVELL ASIA PTE LTD (3)· patent assignee history

2020Patents assigned to MARVELL INT LTD (3)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	158	1984–2020
GLOBALFOUNDRIES INC	16	2016–2020
FIFIELD JOHN Aself	11	2012–2015
MARVELL ASIA PTE LTD	3	2020–2021
MARVELL INT LTD	3	2020

Locations

Location	Patents	Span
Underhill, VT, US	160	1991–2021
Burlington, VT, US	10	2016–2020
Jericho, VT, US	3	1984–1991
Essex Junction, VT, US	2	2011–2012
Chittenden County, VT, US	1	2002