LexDanaLexDanabeta
Inventor

Mou-Shiung Lin

Inventor
Hsinchu, TW

Overview

312→
Patents
1994–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 312 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1047%
H10DInorganic electric semiconductor devices22%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h107%
Y10TTechnical subjects covered by former us classification6%
H01LSemiconductor devices4%
H03KPulse technique2%
G01RMeasuring electric variables2%
G06FElectric digital data processing2%
G11CStatic stores1%
H05KPrinted circuits1%
PatentTitleYear
10,872,413Method for data management and machine learning with fine resolution202010,819,345Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells202010,727,837Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells202010,630,296Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells202010,623,000Logic drive using standard commodity programmable logic IC chips202010,608,638Logic drive using standard commodity programmable logic IC chips202010,608,642Logic drive using standard commodity programmable logic IC chips comprising non-volatile radom access memory cells202010,594,322Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells202010,523,210Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells201910,489,544Logic drive based on standard commodity FPGA IC chips201910,483,979Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells201910,447,274Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells20199,899,284'Chip package and method for fabricating the same'20189,810,684'Method for increasing number of stem cells in human or animal bodies'20179,612,615'Integrated circuit chip using top post-passivation technology and bottom structure technology'20179,391,021'Chip package and method for fabricating the same'20169,153,555'Method of wire bonding over active area of a semiconductor circuit'20159,142,527'Method of wire bonding over active area of a semiconductor circuit'20159,136,246'Integrated chip package structure using silicon substrate and method of manufacturing the same'20159,030,029'Chip package with die and substrate'20159,018,774'Chip package'20158,912,666'Structure and manufacturing method of chip scale package'20148,901,733'Reliable metal bumps on top of I/O pads after removal of test probe marks'20148,884,433'Circuitry component and method for forming the same'20148,853,754'Image and light sensor chip packages'20148,835,221'Integrated chip package structure using ceramic substrate and method of manufacturing the same'20148,809,951'Chip packages having dual DMOS devices with power management integrated circuits'20148,804,360'System-in packages'20148,749,021'Voltage regulator integrated with semiconductor chip'20148,748,227'Method of fabricating chip package'20148,742,580'Method of wire bonding over active area of a semiconductor circuit'20148,742,582'Solder interconnect on IC chip'20148,692,374'Carbon nanotube circuit component structure'20148,618,580'Integrated circuit chips with fine-line metal and over-passivation metal'20138,581,404'Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures'20138,558,383'Post passivation structure for a semiconductor device and packaging process for same'20138,552,559'Very thick metal interconnection scheme in IC chips'20138,546,947'Chip structure and process for forming the same'20138,535,976'Method for fabricating chip package with die and substrate'20138,531,038'Top layers of metal for high performance IC\'s'20138,519,552'Chip structure'20138,503,186'System-in packages'20138,492,900'Post passivation interconnection schemes on top of IC chip'20138,492,870'Semiconductor package with interconnect layers'20138,487,400'High performance system-on-chip using post passivation process'20138,482,127'Post passivation interconnection schemes on top of IC chip'20138,471,384'Top layers of metal for high performance IC\'s'20138,471,361'Integrated chip package structure using organic substrate and method of manufacturing the same'20138,471,389'Multiple selectable function integrated circuit module'20138,471,388'Integrated circuit and method for fabricating the same'20138,461,686'Post passivation interconnection schemes on top of IC chip'20138,456,013'Post passivation interconnection schemes on top of the IC chips'20138,456,856'Integrated circuit chip using top post-passivation technology and bottom structure technology'20138,440,272'Method for forming post passivation Au layer with clean surface'20138,435,883'Post passivation interconnection schemes on top of IC chips'20138,436,449'Chip package and method for fabricating the same'20138,426,958'Stacked chip package with redistribution lines'20138,426,982'Structure and manufacturing method of chip scale package'20138,421,222'Chip package having a chip combined with a substrate via a copper pillar'20138,421,158'Chip structure with a passive device and method for forming the same'20138,420,520'Non-cyanide gold electroplating for fine-line gold traces and gold pads'20138,421,227'Semiconductor chip structure'20138,415,800'Top layers of metal for high performance IC\'s'20138,399,988'High performance sub-system design and assembly'20138,399,989'Metal pad or metal bump over pad exposed by passivation layer'20138,384,508'Method for making high-performance RF integrated circuits'20138,373,202'Integrated circuit chips with fine-line metal and over-passivation metal'20138,368,150'High performance IC chip having discrete decoupling capacitors attached to its IC surface'20138,368,193'Chip package'20138,368,213'Low fabrication cost, fine pitch and high reliability solder bump'20138,368,204'Chip structure and process for forming the same'20138,362,588'Semiconductor chip with coil element over passivation layer'20138,350,386'Top layers of metal for high performance IC\'s'20138,344,524'Wire bonding method for preventing polymer cracking'20138,319,354'Semiconductor chip with post-passivation scheme formed over passivation layer'20128,304,907'Top layers of metal for integrated circuits'20128,304,766'Semiconductor chip with a bonding pad having contact and test areas'20128,294,279'Chip package with dam bar restricting flow of underfill'2012RE043674'Post passivation metal scheme for high-performance integrated circuit devices'20128,242,601'Semiconductor chip with passivation layer comprising metal interconnect and contact pads'20128,232,192'Process of bonding circuitry components'20128,211,791'Method for fabricating circuitry component'20128,198,729'Connection between a semiconductor chip and a circuit component with a large contact area'20128,193,555'Image and light sensor chip packages'20128,187,965'Wirebond pad for semiconductor chip or wafer'20128,188,603'Post passivation interconnection schemes on top of IC chip'20128,178,435'High performance system-on-chip inductor using post passivation process'20128,168,527'Semiconductor chip and method for fabricating the same'20128,164,171'System-in packages'20128,159,070'Chip packages'20128,158,508'Structure and manufacturing method of a chip scale package'20128,159,074'Chip structure'20128,148,822'Bonding pad on IC substrate and method for making the same'20128,148,806'Multiple chips bonded to packaging structure with low noise and multiple selectable functions'20128,138,079'Method of wire bonding over active area of a semiconductor circuit'20128,129,265'High performance system-on-chip discrete components using post passivation process'20128,124,446'Structure of high performance combo chip and processing method'20128,119,446'Integrated chip package structure using metal substrate and method of manufacturing the same'20128,120,181'Post passivation interconnection process and structures'20128,107,311'Software programmable multiple function integrated circuit module'20128,089,155'High performance system-on-chip discrete components using post passivation process'20128,072,070'Low fabrication cost, fine pitch and high reliability solder bump'20118,067,837'Metallization structure over passivation layer for IC chip'20118,044,475'Chip package'20118,035,227'Top layers of metal for high performance IC\'s'20118,030,775'Wirebond over post passivation thick metal'20118,026,588'Method of wire bonding over active area of a semiconductor circuit'20118,021,921'Method of joining chips utilizing copper pillar'20118,021,918'Integrated circuit chips with fine-line metal and over-passivation metal'20118,022,546'Top layers of metal for high performance IC\'s'20118,022,552'Integrated circuit and method for fabricating the same'20118,022,544'Chip structure'20118,022,545'Top layers of metal for high performance IC\'s'20118,018,060'Post passivation interconnection process and structures'20118,013,448'Multiple selectable function integrated circuit module'20118,013,449'Post passivation interconnection schemes on top of the IC chips'20118,008,776'Chip structure and process for forming the same'20118,008,775'Post passivation interconnection structures'20118,004,083'Integrated circuit chips with fine-line metal and over-passivation metal'20118,004,092'Semiconductor chip with post-passivation scheme formed over passivation layer'20118,004,088'Post passivation interconnection schemes on top of IC chip'20117,999,381'High performance sub-system design and assembly'20117,999,384'Top layers of metal for high performance IC\'s'20117,990,037'Carbon nanotube circuit component structure'20117,989,954'Integrated circuit chips with fine-line metal and over-passivation metal'20117,985,653'Semiconductor chip with coil element over passivation layer'20117,977,763'Chip package with die and substrate'20117,973,401'Stacked chip package with redistribution lines'20117,973,629'Method for making high-performance RF integrated circuits'20117,968,372'Method of joining chips utilizing copper pillar'20117,969,006'Integrated circuit chips with fine-line metal and over-passivation metal'20117,964,973'Chip structure'20117,960,212'Structure of high performance combo chip and processing method'20117,960,269'Method for forming a double embossing structure'20117,960,825'Chip package and method for fabricating the same'20117,960,842'Structure of high performance combo chip and processing method'20117,947,978'Semiconductor chip with bond area'20117,932,603'Chip structure and process for forming the same'20117,932,172'Semiconductor chip and process for forming the same'20117,928,576'Post passivation interconnection schemes on top of the IC chips'20117,923,848'High performance sub-system design and assembly'20117,923,366'Post passivation interconnection schemes on top of IC chip'20117,919,412'Over-passivation process of forming polymer layer over IC chip'20117,919,865'Post passivation interconnection schemes on top of IC chip'20117,919,867'Chip structure and process for forming the same'20117,919,873'Structure of high performance combo chip and processing method'20117,915,157'Chip structure and process for forming the same'20117,915,734'Chip structure and process for forming the same'20117,915,161'Post passivation interconnection schemes on top of IC chip'20117,906,422'Chip structure and process for forming the same'20117,906,849'Chip structure and process for forming the same'20117,902,679'Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump'20117,902,067'Post passivation interconnection schemes on top of the IC chips'20117,898,058'Integrated chip package structure using organic substrate and method of manufacturing the same'20117,892,965'Post passivation interconnection schemes on top of IC chip'20117,884,479'Top layers of metal for high performance IC\'s'20117,880,304'Post passivation interconnection schemes on top of the IC chips'20117,868,454'High performance sub-system design and assembly'20117,868,463'High performance sub-system design and assembly'20117,863,654'Top layers of metal for high performance IC\'s'20117,863,739'Low fabrication cost, fine pitch and high reliability solder bump'20117,592,205'Over-passivation process of forming polymer layer over IC chip'20097,582,966'Semiconductor chip and method for fabricating the same'2009RE040887'Semiconductor chip with redistribution metal layer'20097,582,556'Circuitry component and method for forming the same'20097,569,422'Chip package and method for fabricating the same'20097,554,208'Wirebond pad for semiconductor chip or wafer'20097,547,969'Semiconductor chip with passivation layer comprising metal interconnect and contact pads'20097,534,718'Post passivation interconnection schemes on top of IC chips'20097,535,102'High performance sub-system design and assembly'20097,531,417'High performance system-on-chip passive device using post passivation process'20097,524,759'Post passivation interconnection schemes on top of IC chip'20097,521,805'Post passivation interconnection schemes on top of the IC chips'20097,521,812'Method of wire bonding over active area of a semiconductor circuit'20097,517,778'Structure of high performance combo chip and processing method'20097,511,376'Circuitry component with metal layer over die and extending to place not over die'20097,508,059'Stacked chip package with redistribution lines'20097,498,255'Post passivation interconnection schemes on top of the IC chips'20097,498,196'Structure and manufacturing method of chip scale package'20097,495,304'Chip package'20097,482,268'Top layers of metal for integrated circuits'20097,482,259'Chip structure and process for forming the same'20097,482,693'Top layers of metal for high performance IC\'s'20097,479,450'Post passivation interconnection schemes on top of the IC chips'20097,473,999'Semiconductor chip and process for forming the same'20097,470,997'Wirebond pad for semiconductor chip or wafer'20087,470,988'Chip structure and process for forming the same'20087,470,927'Semiconductor chip with coil element over passivation layer'20087,468,551'Multiple chips bonded to packaging structure with low noise and multiple selectable functions'20087,468,316'Low fabrication cost, fine pitch and high reliability solder bump'20087,468,545'Post passivation structure for a semiconductor device and packaging process for same'20087,465,653'Reliable metal bumps on top of I/O pads after removal of test probe marks'20087,465,975'Top layers of metal for high performance IC\'s'20087,466,007'Post passivation interconnection schemes on top of IC chip'20087,465,654'Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures'20087,462,938'Post passivation interconnection schemes on top of IC chip'20087,462,558'Method for fabricating a circuit component'20087,459,791'Post passivation interconnection schemes on top of IC chip'20087,459,790'Post passivation interconnection schemes on top of the IC chips'20087,459,761'High performance system-on-chip using post passivation process'20087,456,100'Top layers of metal for high performance IC\'s'20087,452,803'Method for fabricating chip structure'20087,449,752'Post passivation interconnection schemes on top of the IC chips'20087,446,035'Post passivation interconnection schemes on top of IC chips'20087,446,031'Post passivation interconnection schemes on top of IC chips'20087,443,034'Post passivation interconnection schemes on top of the IC chips'20087,442,969'Top layers of metal for high performance IC\'s'20087,443,033'Post passivation interconnection schemes on top of the IC chips'20087,439,626'Post passivation interconnection schemes on top of IC chip'20087,439,627'Post passivation interconnection schemes on top of the IC chips'20087,427,560'Top layers of metal for high performance IC\'s'20087,425,767'Chip structure with redistribution traces'20087,425,764'Top layers of metal for high performance IC\'s'20087,422,941'High performance system-on-chip using post passivation process'20087,422,976'Top layers of metal for high performance IC\'s'20087,423,346'Post passivation interconnection process and structures'20087,420,276'Post passivation structure for semiconductor chip or wafer'20087,419,900'Post passivation interconnection schemes on top of the IC chips'20087,416,971'Top layers of metal for integrated circuits'20087,417,317'Post passivation interconnection schemes on top of the IC chips'20087,413,929'Integrated chip package structure using organic substrate and method of manufacturing the same'20087,405,149'Post passivation method for semiconductor chip or wafer'20087,405,150'Post passivation interconnection schemes on top of the IC chips'20087,397,121'Semiconductor chip with post-passivation scheme formed over passivation layer'20087,397,117'Chip package with die and substrate'20087,396,756'Top layers of metal for high performance IC\'s'20087,397,135'Top layers of metal for high performance IC\'s'20087,388,292'Top layers of metal for high performance IC\'s'20087,384,864'Top layers of metal for high performance IC\'s'20087,385,292'Top layers of metal for high performance IC\'s'20087,385,291'Top layers of metal for high performance IC\'s'20087,382,052'Post passivation interconnection schemes on top of IC chip'20087,382,005'Circuit component with bump formed over chip'20087,381,642'Top layers of metal for integrated circuits'20087,382,058'Top layers of metal for high performance IC\'s'20087,378,735'High performance sub-system design and assembly'20087,372,162'Multiple selectable function integrated circuit module'20087,372,085'Top layers of metal for high performance IC\'s'20087,372,155'Top layers of metal for high performance IC\'s'20087,372,161'Post passivation interconnection schemes on top of the IC chips'20087,368,376'Top layers of metal for high performance IC\'s'20087,358,610'Top layers of metal for high performance IC\'s'20087,360,005'Software programmable multiple function integrated circuit module'20087,355,282'Post passivation interconnection process and structures'20087,351,650'Post passivation interconnection schemes on top of the IC chips'20087,345,365'Electronic component with die and passive device'20087,329,954'Top layers of metal for high performance IC\'s'20087,319,377'Method for making high-performance RF integrated circuits'20087,319,277'Chip structure with redistribution traces'20087,309,920'Chip structure and process for forming the same'20077,297,614'Method for fabricating circuitry component'20077,294,870'Top layers of metal for high performance IC\'s'20077,294,871'Top layers of metal for high performance IC\'s'20077,288,845'Fabrication of wire bond pads over underlying active devices, passive devices and/or dielectric layers in integrated circuits'20077,276,422'Post passivation interconnection schemes on top of the IC chips'20077,271,033'Method for fabricating chip package'20077,271,489'Post passivation interconnection schemes on top of the IC chips'20077,265,047'Post passivation interconnection schemes on top of the IC chips'20077,247,932'Chip package with capacitor'20077,242,099'Chip package with multiple chips connected by bumps'20077,230,340'Post passivation interconnection schemes on top of the IC chips'20077,205,646'Electronic device and chip package'20077,045,901'Chip-on-chip connection with second chip located in rectangular open window hole in printed circuit board'20066,965,165'Top layers of metal for high performance IC\'s'20056,939,747'Multiple selectable function integrated circuit module'20056,936,531'Process of fabricating a chip structure'20056,897,507'Capacitor for high performance system-on-chip using post passivation device'20056,869,870'High performance system-on-chip discrete components using post passivation process'20056,818,545'Low fabrication cost, fine pitch and high reliability solder bump'20046,815,324'Reliable metal bumps on top of I/O pads after removal of test probe marks'20046,800,941'Integrated chip package structure using ceramic substrate and method of manufacturing the same'20046,798,073'Chip structure and process for forming the same'20046,791,192'Multiple chips bonded to packaging structure with low noise and multiple selectable functions'20046,768,208'Multiple chips bonded to packaging structure with low noise and multiple selectable functions'20046,762,115'Chip structure and process for forming the same'20046,759,275'Method for making high-performance RF integrated circuits'20046,756,295'Chip structure and process for forming the same'20046,746,898'Integrated chip package structure using silicon substrate and method of manufacturing the same'20046,734,563'Post passivation interconnection schemes on top of the IC chips'20046,700,162'Chip structure to improve resistance-capacitance delay and reduce energy loss of the chip'20046,673,698'Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers'20046,657,310'Top layers of metal for high performance IC\'s'20036,649,509'Post passivation metal scheme for high-performance integrated circuit devices'20036,620,728'Top layers of metal for high performance IC\'s'20036,605,528'Post passivation metal scheme for high-performance integrated circuit devices'20036,593,649'Methods of IC rerouting option for multiple package system applications'20036,586,266'High performance sub-system design and assembly'20036,555,398'Software programmable multiple function integrated circuit module'20036,515,369'High performance system-on-chip using post passivation process'20036,495,442'Post passivation interconnection schemes on top of the IC chips'20026,495,912'Structure of ceramic package with integrated passive devices'20026,489,647'Capacitor for high performance system-on-chip using post passivation process structure'20026,489,656'Resistor for high performance system-on-chip using post passivation process'20026,486,563'Wafer scale packaging scheme'20026,455,885'Inductor structure for high performance system-on-chip using post passivation process'20026,426,556'Reliable metal bumps on top of I/O pads with test probe marks'20026,399,975'Wide bit memory using post passivation interconnection scheme'20026,399,997'High performance system-on-chip using post passivation process and glass substrates'20026,383,916'Top layers of metal for high performance IC\'s'20026,356,958'Integrated circuit module has common function known good integrated circuit die with multiple selectable functions'2002

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1994–2020Based in Hsinchu, TW· patent location history
2001–2007Patents assigned to MEGIC CORP (36)· patent assignee history
2005–2016Patents assigned to LIN MOU-SHIUNG (106)· patent assignee history
2007–2017Patents assigned to MEGICA CORP (207)· patent assignee history
2008–2015Patents assigned to LEE JIN-YUAN (39)· patent assignee history
2008Based in Science-Based Industrial Park, Hsin-Chu, TW· patent location history
2012–2013Patents assigned to CHOU CHIU-MING (16)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MEGICA CORP2072007–2017
LIN MOU-SHIUNGself1062005–2016
LEE JIN-YUAN392008–2015
MEGIC CORP362001–2007
CHOU CHIU-MING162012–2013
Locations
LocationPatentsSpan
Hsinchu, TW3111994–2020
Science-Based Industrial Park, Hsin-Chu, TW12008