Inventor
Brad Sharpe-Geisler
Inventor
San Jose, CA, US
Overview
Patents· 29 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Kprimary
H03KPulse technique44%
G06FElectric digital data processing19%
G11CStatic stores15%
G01RMeasuring electric variables4%
H02HEmergency protective circuit arrangements4%
H03MCoding4%
G05FSystems for regulating electric or magnetic variables2%
H01LSemiconductor devices2%
H04LTransmission of digital information, e.g. telegraphic communication2%
H10DInorganic electric semiconductor devices2%
PatentTitleYear
10,630,269Multiple mode device implementation for programmable logic devices202010,417,078Deterministic read back and error detection for programmable logic devices201910,382,021Flexible ripple mode device implementation for programmable logic devices201910,141,917Multiple mode device implementation for programmable logic devices201810,079,054Selective power gating of routing resource configuration memory bits for programmable logic devices20189,735,761'Flexible ripple mode device implementation for programmable logic devices'20179,716,491'Multiple mode device implementation for programmable logic devices'20179,543,950'High speed complementary NMOS LUT logic'20179,537,308'ESD protection using shared RC trigger'20179,515,643'Hot-socket circuitry'20169,287,872'PVT compensation scheme for output buffers'20169,252,755'Shared logic for multiple registers with asynchronous initialization'20168,971,146'Dual-port SRAM with bit line clamping'20158,643,168'Integrated circuit package with input capacitance compensation'20148,451,679'Dual-port SRAM with bit line clamping'20137,868,646'Soft error upset hardened integrated circuit systems and methods'20117,787,326'Programmable logic device with a multi-data rate SDRAM interface'20107,741,865'Soft error upset hardened integrated circuit systems and methods'20107,576,563'High fan-out signal routing systems and methods'20097,558,143'Programmable logic device with power-saving architecture'20097,459,935'Programmable logic devices with distributed memory'20087,411,419'Input/output systems and methods'20087,376,037'Programmable logic device with power-saving architecture'20087,355,441'Programmable logic devices with distributed memory and non-volatile memory'20087,342,838'Programmable logic device with a double data rate SDRAM interface'20087,256,613'Programmable interconnect architecture for programmable logic devices'20077,098,685'Scalable serializer-deserializer architecture and programmable interface'20066,028,789'Zero-power CMOS non-volatile memory cell having an avalanche injection element'20005,189,322'Low-power sense amplifier with feedback'1993Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1993Patents assigned to ADVANCED MICRO DEVICES INC (1)· patent assignee history
1993–2020Based in San Jose, CA, US· patent location history
2006–2020Patents assigned to LATTICE SEMICONDUCTOR CORP (27)· patent assignee history
2013Patents assigned to FONTANA FABIANO (1)· patent assignee history
2013Patents assigned to SHARPE-GEISLER BRAD (1)· patent assignee history
2016Patents assigned to LATTICESEMICONDUCTORCORPORATION (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| LATTICE SEMICONDUCTOR CORP | 27 | 2006–2020 |
| ADVANCED MICRO DEVICES INC | 1 | 1993 |
| FONTANA FABIANO | 1 | 2013 |
| LATTICESEMICONDUCTORCORPORATION | 1 | 2016 |
| SHARPE-GEISLER BRADself | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 29 | 1993–2020 |