Inventor

Ruen-Rone Lee

Inventor

Hsinchu, TW

Overview

18→

Patents

1998–2015

Patent span

Physics

Primary field (CPC G)

Patents· 18 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Tprimary

G06TImage data processing or generation, in general52%

H04NPictorial communication, e.g. television26%

G09GArrangements or circuits for control of indicating devices using static means to present variable information13%

G06FElectric digital data processing4%

G06KGraphical data reading4%

PatentTitleYear

9,016,571'Two dimensional code and method of creating the same'2015 8,576,220'Image processing method and associated apparatus for rendering three-dimensional effect using two-dimensional image'2013 8,442,346'Image processing method and associated apparatus for adjusting an edge pixel'2013 7,330,182'3D graphics processing method'2008 7,129,952'Core logic circuit of computer system capable of accelerating 3D graphics'2006 7,126,990'Method and apparatus for controlling a stereo video display with non-stereo video source'2006 7,085,016'Method and apparatus for dithering and inversely dithering in image processing and computer graphics'2006 7,034,819'Apparatus and method for generating an interleaved stereo image'2006 7,027,664'Method for removing noise regions in stereo 3D display system'2006 6,956,964'Apparatus for producing real-time anaglyphs'2005 6,774,906'Method and system of improving silhouette appearance in bump mapping'2004 6,690,384'System and method for full-scene anti-aliasing and stereo three-dimensional display control'2004 6,466,208'Apparatus and method for adjusting 3D stereo video transformation'2002 6,377,273'Fast area-coverage computing method for anti-aliasing in graphics'2002 6,057,861'Mip map/rip map texture linear addressing memory organization and address generator'2000 5,963,220'Mip map/rip map texture linear addressing memory organization and address generator'1999 5,946,005'Computer graphics memory architecture having a graphics processor and a buffer'1999 5,751,290'Three dimensional graphics system and method with correction to z buffer value errors'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1998–2002Patents assigned to IND TECH RES INST (5)· patent assignee history

1998–2015Based in Hsinchu, TW· patent location history

2002–2006Patents assigned to SILICON INTEGRATED SYS CORP (6)· patent assignee history

2004–2005Patents assigned to SILICON INTERGRATED SYSTEMS CO (2)· patent assignee history

2006Based in Hsin Chu, TW· patent location history

2008Based in Taipei, TW· patent location history

2013Patents assigned to LEE RUEN-RONE (2)· patent assignee history

2013Patents assigned to MSTAR SEMICONDUCTOR INC (2)· patent assignee history

2013Based in Hsinchu County, TW· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
SILICON INTEGRATED SYS CORP	6	2002–2006
IND TECH RES INST	5	1998–2002
LEE RUEN-RONEself	2	2013
MSTAR SEMICONDUCTOR INC	2	2013
SILICON INTERGRATED SYSTEMS CO	2	2004–2005

Locations

Location	Patents	Span
Hsinchu, TW	13	1998–2015
Hsinchu County, TW	2	2013
Hsin Chu, TW	2	2006
Taipei, TW	1	2008