Inventor
Tsing-Chow Wang
Inventor
Cupertino, CA, US
Overview
Patents· 28 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1041%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests16%
H03KPulse technique8%
H05KPrinted circuits6%
H10NElectric solid-state devices not otherwise provided for4%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h104%
Y02PClimate change mitigation technologies in the production or processing of goods4%
B23KSoldering or unsoldering2%
G02BOptical elements, systems or apparatus2%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices2%
PatentTitleYear
9,129,883'Package structure of optical transceiver component'20158,721,194'Optical transceiver module'20147,875,505'Multi-die semiconductor package structure and method for manufacturing the same'20117,838,411'Fluxless reflow process for bump formation'20107,816,787'Method of forming low stress multi-layer metallurgical structures and high reliable lead free solder termination electrodes'20107,462,556'Method of forming low stress multi-layer metallurgical structures and high reliable lead free solder termination electrodes'20087,381,636'Planar bond pad design and method of making the same'20087,053,490'Planar bond pad design and method of making the same'20066,784,089'Flat-top bumping structure and preparation method'20046,674,173'Stacked paired die package and method of making the same'20046,635,585'Method for forming patterned polyimide layer'20036,544,878'Microelectronic fabrication having formed therein terminal electrode structure providing enhanced barrier properties'20036,448,171'Microelectronic fabrication having formed therein terminal electrode structure providing enhanced passivation and enhanced bondability'20026,424,037'Process to make a tall solder ball by placing a eutectic solder ball on top of a high lead solder ball'20026,362,087'Method for fabricating a microelectronic fabrication having formed therein a redistribution structure'20026,316,831'Microelectronic fabrication having formed therein terminal electrode structure providing enhanced barrier properties'20016,281,041'Process to make a tall solder ball by placing a eutectic solder ball on top of a high lead solder ball'20015,587,336'Bump formation on yielded semiconductor dies'19965,414,299'Semi-conductor device interconnect package assembly for improved package performance'19955,386,141'Leadframe having one or more power/ground planes without vias'19955,171,712'Method of constructing termination electrodes on yielded semiconductor die by visibly aligning the die pads through a transparent substrate'19924,559,459'High gain non-linear threshold input Josephson junction logic circuit'19854,509,146'High density Josephson junction memory circuit'19854,501,975'Josephson junction latch circuit'19854,458,160'High gain Josephson junction voltage amplifier'19844,437,227'Method of making improved tunnel barriers for superconducting Josephson junction devices'19844,413,197'Four Josephson junction direct-coupled and gate circuit'19834,413,196'Three Josephson junction direct coupled isolation circuit'1983Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1983–1985Patents assigned to SPERRY CORP (7)· patent assignee history
1983–1985Based in Norristown, PA, US· patent location history
1992–1995Patents assigned to VLSI TECHNOLOGY INC (3)· patent assignee history
1992–1996Based in San Jose, CA, US· patent location history
2001–2004Patents assigned to APTOS CORP (9)· patent assignee history
2001–2004Based in Cupertino, CA, US· patent location history
2006–2011Patents assigned to SEMICONDUCTOR MFG INT SHANGHAI (6)· patent assignee history
2006–2011Based in Shanghai, CN· patent location history
2014–2015Patents assigned to LUXNET CORP (2)· patent assignee history
2015Based in Zhongli City, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| APTOS CORP | 9 | 2001–2004 |
| SPERRY CORP | 7 | 1983–1985 |
| SEMICONDUCTOR MFG INT SHANGHAI | 6 | 2006–2011 |
| VLSI TECHNOLOGY INC | 3 | 1992–1995 |
| LUXNET CORP | 2 | 2014–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Cupertino, California, US | 9 | 2001–2004 |
| Norristown, Pennsylvania, US | 7 | 1983–1985 |
| Shanghai, CN | 6 | 2006–2011 |
| San Jose, California, US | 4 | 1992–1996 |
| Zhongli City, TW | 1 | 2015 |