Inventor
Satyendranath Mukherjee
Inventor
Yorktown Heights, NY, US
Overview
Patents· 16 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices44%
H10BElectronic memory devices15%
H03KPulse technique11%
G11CStatic stores7%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems7%
G01RMeasuring electric variables4%
G02FOptical devices or arrangements for the control of light by modification of the optical properties of the media of the elements involved therein4%
G09FDisplaying4%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h104%
PatentTitleYear
6,559,068'Method for improving inversion layer mobility in a silicon carbide metal-oxide semiconductor field-effect transistor'20036,011,278'Lateral silicon carbide semiconductor device having a drift region with a varying doping level'20005,751,038'Electrically erasable and programmable read only memory (EEPROM) having multiple overlapping metallization layers'19985,606,521'Electrically erasable and programmable read only memory with non-uniform dielectric thickness'19975,486,485'Method of manufacturing a reflective display'19965,485,292'High voltage differential sensor having a capacitive attenuator'19965,446,300'Semiconductor device configuration with multiple HV-LDMOS transistors and a floating well circuit'19955,374,571'Vertical power MOS device with increased ruggedness and method of fabrication'19945,268,586'Vertical power MOS device with increased ruggedness and method of fabrication'19935,243,214'Power integrated circuit with latch-up prevention'19935,229,312'Nonvolatile trench memory device and self-aligned method for making such a device'19935,146,426'Electrically erasable and programmable read only memory with trench structure'19925,034,790'MOS transistor with semi-insulating field plate and surface-adjoining top layer'19914,939,566'Semiconductor switch with parallel DMOS and IGT'19904,926,074'Semiconductor switch with parallel lateral double diffused MOS transistor and lateral insulated gate transistor'19904,893,212'Protection of power integrated circuits against load voltage surges'1990Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1990–1996Patents assigned to PHILIPS CORP (11)· patent assignee history
1990–2003Based in Yorktown Heights, NY, US· patent location history
1990–1997Based in Yorktown, NY, US· patent location history
1996Patents assigned to PHILIP ELECTRONICS NORTH AMERI (1)· patent assignee history
1997–2000Patents assigned to PHILIPS ELECTRONICS NA (3)· patent assignee history
1998Based in Yortown Heights, NY, US· patent location history
2003Patents assigned to KONINKL PHILIPS ELECTRONICS NV (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| PHILIPS CORP | 11 | 1990–1996 |
| PHILIPS ELECTRONICS NA | 3 | 1997–2000 |
| KONINKL PHILIPS ELECTRONICS NV | 1 | 2003 |
| PHILIP ELECTRONICS NORTH AMERI | 1 | 1996 |
Locations
| Location | Patents | Span |
|---|---|---|
| Yorktown Heights, New York, US | 12 | 1990–2003 |
| Yorktown, New York, US | 3 | 1990–1997 |
| Yortown Heights, New York, US | 1 | 1998 |