Inventor
Pin-Nan Tseng
Inventor
Hsinchu, TW
Overview
Patents· 17 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1038%
H10DInorganic electric semiconductor devices21%
H01LSemiconductor devices17%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation8%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h108%
B24BMachines, devices, or processes for grinding or polishing4%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
PatentTitleYear
10,510,597Methods for hybrid wafer bonding integrated with CMOS processing201910,453,889Dual facing BSI image sensors with wafer level stacking20199,728,453'Methods for hybrid wafer bonding integrated with CMOS processing'20179,711,555'Dual facing BSI image sensors with wafer level stacking'20176,448,649'Multi-layer wiring structure having conductive sidewall etch stoppers and a stacked plug interconnect'20026,169,314'Layout pattern for improved MOS device matching'20015,952,698'Layout pattern for improved MOS device matching'19995,866,481'Selective partial curing of spin-on-glass by ultraviolet radiation to protect integrated circuit dice near the wafer edge'19995,801,096'Self-aligned tungsen etch back process to minimize seams in tungsten plugs'19985,756,396'Method of making a multi-layer wiring structure having conductive sidewall etch stoppers and a stacked plug interconnect'19985,723,893'Method for fabricating double silicide gate electrode structures on CMOS-field effect transistors'19985,712,207'Profile improvement of a metal interconnect structure on a tungsten plug'19985,702,982'Method for making metal contacts and interconnections concurrently on semiconductor integrated circuits'19975,575,706'Chemical/mechanical planarization (CMP) apparatus and polish method'19965,547,881'Method of forming a resistor for ESD protection in a self aligned silicide process'19965,521,121'Oxygen plasma etch process post contact layer etch back'19965,411,907'Capping free metal silicide integrated process'1995Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1995–2002Patents assigned to TAIWAN SEMICONDUCTOR MFG (13)· patent assignee history
1995Based in Taoyuan, TW· patent location history
1996–2019Based in Hsinchu, TW· patent location history
2017–2019Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (4)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG | 13 | 1995–2002 |
| TAIWAN SEMICONDUCTOR MFG CO LTD | 4 | 2017–2019 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu, TW | 16 | 1996–2019 |
| Taoyuan, TW | 1 | 1995 |