Inventor
An-Chung Chen
Inventor
Sunnyvale, CA, US
Overview
Patents· 24 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores24%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses12%
H04LTransmission of digital information, e.g. telegraphic communication12%
H10BElectronic memory devices12%
H10NElectric solid-state devices not otherwise provided for12%
G06FElectric digital data processing10%
G05FSystems for regulating electric or magnetic variables5%
H01LSemiconductor devices5%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%
H04BTransmission2%
PatentTitleYear
10,627,851Reference clock signal generation method, memory storage device and connection interface unit20209,449,660'Sampling circuit module, memory control circuit unit, and method for sampling data'20169,391,119'Non-volatile random access memory devices with shared transistor configuration and methods of forming the same'20169,237,005'Clock data recovery circuit module and method for generating data recovery clock'20169,058,863'Reference frequency setting method, memory controller and memory storage apparatus'20159,059,789'Signal processing method, connector, and memory storage device'20159,020,086'Clock data recovery circuit module and method for generating data recovery clock'20159,003,100'Reference frequency setting method, memory controller, and flash memory storage apparatus'20158,803,120'Diode and resistive memory device structures'20148,787,515'Clock data recovery circuit'20148,571,158'Method and data transceiving system for generating reference clock signal'20138,084,770'Test structures for development of metal-insulator-metal (MIM) devices'20118,035,099'Diode and resistive memory device structures'20117,916,523'Method of erasing a resistive memory device'20117,746,698'Programming in memory devices using source bitline voltage bias'20107,646,624'Method of selecting operating characteristics of a resistive memory device'20107,619,401'Bandgap reference circuit'20097,468,525'Test structures for development of metal-insulator-metal (MIM) devices'20087,384,800'Method of fabricating metal-insulator-metal (MIM) device with stable data retention'20087,289,351'Method of programming a resistive memory device'20077,286,388'Resistive memory device with improved data retention'20077,253,599'Bandgap reference circuit'20076,681,271'Computer system for multi-type DRAM support'20045,778,196'Method and device for identifying a bus memory region'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004–2007Based in Taipei, TW· patent location history
2007–2014Patents assigned to SPANSION LLC (10)· patent assignee history
2007–2014Based in Sunnyvale, CA, US· patent location history
2011–2014Patents assigned to AVANZINO STEVEN (2)· patent assignee history
2011–2014Patents assigned to CHEN AN (2)· patent assignee history
2013–2020Patents assigned to PHISON ELECTRONICS CORP (9)· patent assignee history
2013–2015Patents assigned to CHEN AN-CHUNG (3)· patent assignee history
2013–2016Based in Hsinchu, TW· patent location history
2016–2020Based in Hsinchu County, TW· patent location history
2016Based in Los Altos, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SPANSION LLC | 10 | 2007–2014 |
| PHISON ELECTRONICS CORP | 9 | 2013–2020 |
| CHEN AN-CHUNGself | 3 | 2013–2015 |
| AVANZINO STEVEN | 2 | 2011–2014 |
| CHEN ANself | 2 | 2011–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Sunnyvale, California, US | 10 | 2007–2014 |
| Hsinchu, TW | 7 | 2013–2016 |
| Hsinchu County, TW | 2 | 2016–2020 |
| Taipei, TW | 2 | 2004–2007 |
| Los Altos, California, US | 1 | 2016 |