Inventor
Changyuan Chen
Inventor
San Ramon, CA, US
Overview
Patents· 38 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores49%
H10BElectronic memory devices15%
H10DInorganic electric semiconductor devices15%
G06FElectric digital data processing12%
G10LSpeech analysis techniques or speech synthesis4%
H01LSemiconductor devices4%
PatentTitleYear
11,048,436Block storage using a hybrid memory device202110,818,366Post write erase conditioning202010,636,501Memory device with reduced neighbor word line interference using adjustable voltage on source-side unselected word line202010,566,059Three dimensional NAND memory device with drain select gate electrode shared between multiple strings202010,553,294Post write erase conditioning202010,535,411System and method for string-based erase verify to create partial good blocks202010,304,551Erase speed based word line control201910,304,559Memory write verification using temperature compensation201910,269,439Post write erase conditioning201910,204,689Non-volatile memory with methods to reduce creep-up field between dummy control gate and select gate201910,074,440Erase for partially programmed blocks in non-volatile memory201810,008,273Cell current based bit line voltage20189,972,396System and method for programming a memory device with multiple writes without an intervening erase20189,892,790'Method of programming a continuous-channel flash memory device'20189,711,231'System solution for first read issue using time dependent read voltages'20179,704,588'Apparatus and method for preconditioning currents to reduce errors in sensing for non-volatile memory'20179,704,595'Self-detecting a heating event to non-volatile storage'20179,583,206'Data storage device having reflow awareness'20179,543,028'Word line dependent temperature compensation scheme during sensing to counteract cross-temperature effect'20179,530,512'Temperature dependent sensing scheme to counteract cross-temperature threshold voltage distribution widening'20169,472,270'Nonvolatile storage reflow detection'20169,449,693'Split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing'2016RE046056'Programming non-volatile storage with fast bit detection and verify skip'20169,201,788'In-situ block folding for nonvolatile memory'20158,886,877'In-situ block folding for nonvolatile memory'20148,830,745'Memory system with unverified program step'20148,780,642'Split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing'20148,456,915'Programming non-volatile storage with fast bit detection and verify skip'20138,174,895'Programming non-volatile storage with fast bit detection and verify skip'20128,164,135'Non-diffusion junction split-gate nonvolatile memory cells and arrays, methods of programming, erasing, and reading thereof, and methods of manufacture'20127,961,511'Hybrid programming methods and systems for non-volatile memory storage elements'20117,826,267'Method and apparatus for reading and programming a non-volatile memory cell in a virtual ground array'20107,808,839'Split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing'20107,723,774'Non-diffusion junction split-gate nonvolatile memory cells and arrays, methods of programming, erasing, and reading thereof, and methods of manufacture'20107,544,569'Bidirectional split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing'20097,358,559'Bi-directional read/program non-volatile floating gate memory array, and method of formation'20087,247,907'Bidirectional split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing'20077,242,051'Split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing'2007Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2007–2018Patents assigned to SILICON STORAGE TECH INC (11)· patent assignee history
2007–2018Based in Sunnyvale, CA, US· patent location history
2012–2017Patents assigned to SANDISK TECHNOLOGIES INC (11)· patent assignee history
2012–2014Patents assigned to CHEN CHANGYUAN (4)· patent assignee history
2014–2020Based in San Ramon, CA, US· patent location history
2016–2020Patents assigned to SANDISK TECHNOLOGIES LLC (14)· patent assignee history
2018–2020Patents assigned to WESTERN DIGITAL TECH INC (6)· patent assignee history
2020Based in San Jose, CA, US· patent location history
2021Based in Bellevue, WA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SANDISK TECHNOLOGIES LLC | 14 | 2016–2020 |
| SANDISK TECHNOLOGIES INC | 11 | 2012–2017 |
| SILICON STORAGE TECH INC | 11 | 2007–2018 |
| WESTERN DIGITAL TECH INC | 6 | 2018–2020 |
| CHEN CHANGYUANself | 4 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Ramon, California, US | 21 | 2014–2020 |
| Sunnyvale, California, US | 15 | 2007–2018 |
| Bellevue, Washington, US | 1 | 2021 |
| San Jose, California, US | 1 | 2020 |