Inventor
John E. Larson
Inventor
Houston, TX, US
Overview
Patents· 48 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing68%
G11CStatic stores12%
H01RElectrically-conductive connections5%
H05KPrinted circuits5%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%
H04LTransmission of digital information, e.g. telegraphic communication3%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%
PatentTitleYear
10,346,089Data processing system having a write request network and a write data network20199,977,750Coherent memory interleaving with uniform latency20189,665,518'Methods and systems for controlling ordered write transactions to multiple devices using switch point networks'20179,632,933'Efficient coherency response mechanism'20179,497,141'Switch point having look-ahead bypass'20169,448,741'Piggy-back snoops for non-coherent memory transactions within distributed processing systems'20167,320,086'Error indication in a raid memory system'20087,155,568'Transaction generator for initialization, rebuild, and verify of memory'20067,120,758'Technique for improving processor performance'20067,116,241'Removable memory cartridge system for use with a server or other processor-based device'20067,044,770'Technique for identifying multiple circuit components'20067,028,213'Error indication in a raid memory system'20067,010,652'Method for supporting multi-level striping of non-homogeneous memory to maximize concurrency'20066,981,095'Hot replace power control sequence logic'20056,975,241'Removable memory cartridge system for use with a server or other processor-based device'20056,961,800'Method for improving processor performance'20056,892,271'Memory module resync'20056,886,048'Techniques for processing out-of-order requests in a processor-based system'20056,862,646'Method and apparatus for eliminating the software generated ready-signal to hardware devices that are not part of the memory coherency domain'20056,854,070'Hot-upgrade/hot-add memory'20056,832,340'Real-time hardware memory scrubbing'20046,823,424'Rebuild bus utilization'20046,785,835'Raid memory'20046,785,785'Method for supporting multi-level stripping of non-homogeneous memory to maximize concurrency'20046,766,469'Hot-replace of memory'20046,747,563'Removable memory cartridge system for use with a server or other processor-based device'20046,715,116'Memory data verify operation'20046,692,293'Technique for identifying multiple circuit components'20046,684,292'Memory module resync'20046,640,282'Hot replace power control sequence logic'20036,608,564'Removable memory cartridge system for use with a server or other processor-based device'20036,517,375'Technique for identifying multiple circuit components'20036,275,885'System and method for maintaining ownership of a processor bus while sending a programmed number of snoop cycles to the processor cache'20016,247,102'Computer system employing memory controller and bridge interface permitting concurrent operation'20016,209,067'Computer system controller and method with processor write posting hold off on PCI master memory request'20015,974,501'Method and apparatus for detecting memory device types'19995,960,459'Memory controller having precharge prediction based on processor and PCI bus cycles'19995,938,739'Memory controller including write posting queues, bus read control logic, and a data contents counter'19995,819,105'System in which processor interface snoops first and second level caches in parallel with a memory access by a bus mastering device'19985,813,038'Memory controller having precharge prediction based on processor and PC bus cycles'19985,781,925'Method of preventing cache corruption during microprocessor pipelined burst operations'19985,778,413'Programmable memory controller having two level look-up for memory timing parameter'19985,721,935'Apparatus and method for entering low power mode in a computer system'19985,701,433'Computer system having a memory controller which performs readahead operations which can be aborted prior to completion'19975,634,112'Memory controller having precharge prediction based on processor and PCI bus cycles'19975,634,073'System having a plurality of posting queues associated with different types of write operations for selectively checking one queue based upon type of read operation'19975,524,235'System for arbitrating access to memory with dynamic priority assignment'19964,930,106'Dual cache RAM for rapid invalidation'1990Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1990Based in Eagan, MN, US· patent location history
1996–2001Patents assigned to COMPAQ COMPUTER CORP (15)· patent assignee history
1996–1999Based in Katy, TX, US· patent location history
1999–2008Based in Houston, TX, US· patent location history
2001Based in Plano, TX, US· patent location history
2003–2008Patents assigned to HEWLETT PACKARD DEVELOPMENT CO (23)· patent assignee history
2016–2019Patents assigned to FREESCALE SEMICONDUCTOR INC (5)· patent assignee history
2016–2017Patents assigned to BANSE MARK A (2)· patent assignee history
2016–2019Based in Round Rock, TX, US· patent location history
2017–2019Patents assigned to NXP USA INC (4)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| HEWLETT PACKARD DEVELOPMENT CO | 23 | 2003–2008 |
| COMPAQ COMPUTER CORP | 15 | 1996–2001 |
| FREESCALE SEMICONDUCTOR INC | 5 | 2016–2019 |
| NXP USA INC | 4 | 2017–2019 |
| BANSE MARK A | 2 | 2016–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Houston, Texas, US | 29 | 1999–2008 |
| Katy, Texas, US | 11 | 1996–1999 |
| Round Rock, Texas, US | 6 | 2016–2019 |
| Plano, Texas, US | 1 | 2001 |
| Eagan, Minnesota, US | 1 | 1990 |