Inventor
Eric J. White
Inventor
Charlotte, VT, US
Overview
Patents· 63 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1020%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1016%
H01LSemiconductor devices9%
H10DInorganic electric semiconductor devices8%
B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems8%
B81BMicrostructural devices or systems, e.g. micromechanical devices6%
C09GPolishing compositions6%
G06FElectric digital data processing6%
C09KMaterials for miscellaneous applications, not provided for elsewhere4%
C25DProcesses for the electrolytic or electrophoretic production of coatings4%
PatentTitleYear
10,589,992Micro-electro-mechanical system (MEMS) structures and design structures202010,589,991Micro-electro-mechanical system (MEMS) structures and design structures202010,549,987Micro-electro-mechanical system (MEMS) structures and design structures202010,438,803Semiconductor structures having low resistance paths throughout a wafer201910,173,889Planar cavity MEMS and related structures, methods of manufacture and design structures201910,177,000Semiconductor structures having low resistance paths throughout a wafer20199,981,842Micro-Electro-Mechanical System (MEMS) structures and design structures20189,969,613Method for forming micro-electro-mechanical system (MEMS) beam structure20189,938,137Micro-electro-mechanical system (MEMS) structures and design structures20189,932,222Micro-electro-mechanical system (MEMS) structures and design structures20189,708,508'Slurry for chemical-mechanical polishing of metals and use thereof'20179,691,623'Semiconductor structures having low resistance paths throughout a wafer'20179,620,371'Semiconductor structures having low resistance paths throughout a wafer'20179,613,853'Copper wire and dielectric with air gaps'20179,478,427'Semiconductor structures having low resistance paths throughout a wafer'20169,406,472'Planar cavity MEMS and related structures, methods of manufacture and design structures'20169,390,969'Integrated circuit and interconnect, and method of fabricating same'20169,312,140'Semiconductor structures having low resistance paths throughout a wafer'20169,269,666'Methods for selective reverse mask planarization and interconnect structures formed thereby'20169,230,914'Copper wire and dielectric with air gaps'20169,159,671'Copper wire and dielectric with air gaps'20159,087,839'Semiconductor structures with metal lines'20159,057,004'Slurry for chemical-mechanical polishing of metals and use thereof'20158,956,903'Planar cavity MEMS and related structures, methods of manufacture and design structures'20158,829,518'Test structure and calibration method'20148,734,665'Slurry for chemical-mechanical polishing of copper and use thereof'20148,710,661'Methods for selective reverse mask planarization and interconnect structures formed thereby'20148,636,917'Solution for forming polishing slurry, polishing slurry and related methods'20148,518,817'Method of electrolytic plating and semiconductor device fabrication'20138,328,892'Solution for forming polishing slurry, polishing slurry and related methods'20128,236,580'Copper contamination detection method and system for monitoring copper contamination'20128,210,904'Slurryless mechanical planarization for substrate reclamation'20128,129,844'Method of forming a metal silicide layer, devices incorporating metal silicide layers and design structures for the devices'20128,093,679'Integrated BEOL thin film resistor'20128,088,690'CMP method'20127,957,917'Copper contamination detection method and system for monitoring copper contamination'20117,902,629'Integrated BEOL thin film resistor'20117,888,142'Copper contamination detection method and system for monitoring copper contamination'20117,851,353'Method of forming a metal silicide layer, devices incorporating metal silicide layers and design structures for the devices'20107,824,568'Solution for forming polishing slurry, polishing slurry and related methods'20107,485,540'Integrated BEOL thin film resistor'20097,245,025'Low cost bonding pad and method of fabricating same'20077,223,697'Chemical mechanical polishing method'20076,822,472'Detection of hard mask remaining on a surface of an insulating layer'20046,818,992'Self-aligned copper silicide formation for improved adhesion/electromigration'20046,812,193'Slurry for mechanical polishing (CMP) of metals and use thereof'20046,394,638'Trench isolation for active areas and first level conductors'20026,355,565'Chemical-mechanical-polishing slurry and method for polishing metal/oxide layers'20026,348,076'Slurry for mechanical polishing (CMP) of metals and use thereof'20026,340,601'Method for reworking copper metallurgy in semiconductor devices'20026,294,105'Chemical mechanical polishing slurry and method for polishing metal/oxide layers'20016,251,775'Self-aligned copper silicide formation for improved adhesion/electromigration'20016,186,873'Wafer edge cleaning'20016,063,687'Formation of trench isolation for active areas and first level conductors'20005,734,192'Trench isolation for active areas and first level conductors'19985,666,000'Microcavity capacitive device'19975,665,655'Process for producing crackstops on semiconductor devices and devices containing the crackstops'19975,576,246'Personalized area leadframe coining or half etching for reduced mechanical stress at device edge'19965,545,921'Personalized area leadframe coining or half etching for reduced mechanical stress at device edge'19965,530,280'Process for producing crackstops on semiconductor devices and devices containing the crackstops'19965,514,832'Microcavity structures, fabrication processes, and applications thereof'19965,508,234'Microcavity structures, fabrication processes, and applications thereof'19965,294,570'Reduction of foreign particulate matter on semiconductor wafers'1994Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1994–2020Patents assigned to IBM (59)· patent assignee history
1994–1997Based in Essex Junction, VT, US· patent location history
1996–2000Based in Ferrisburg, VT, US· patent location history
2001–2020Based in Charlotte, VT, US· patent location history
2002Based in North Troy, VT, US· patent location history
2012–2016Patents assigned to WHITE ERIC J (12)· patent assignee history
2012–2016Patents assigned to STAMPER ANTHONY K (6)· patent assignee history
2012–2016Patents assigned to HE ZHONG-XIANG (5)· patent assignee history
2016–2019Patents assigned to GLOBALFOUNDRIES INC (5)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 59 | 1994–2020 |
| WHITE ERIC Jself | 12 | 2012–2016 |
| STAMPER ANTHONY K | 6 | 2012–2016 |
| GLOBALFOUNDRIES INC | 5 | 2016–2019 |
| HE ZHONG-XIANG | 5 | 2012–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Charlotte, VT, US | 52 | 2001–2020 |
| Ferrisburg, VT, US | 5 | 1996–2000 |
| Essex Junction, VT, US | 5 | 1994–1997 |
| North Troy, VT, US | 1 | 2002 |