Inventor

Hang T. Nguyen

Inventor

Tempe, AZ, US

Overview

1988–2020

Patent span

Physics

Primary field (CPC G)

Patents· 55 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing55%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use19%

G05FSystems for regulating electric or magnetic variables9%

Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications5%

C09KMaterials for miscellaneous applications, not provided for elsewhere2%

E21BEarth or rock drilling2%

H04LTransmission of digital information, e.g. telegraphic communication2%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%

B08BCleaning in general1%

G11BInformation storage based on relative movement between record carrier and transducer1%

PatentTitleYear

10,613,620Providing per core voltage and frequency control2020 10,345,884Mechanism to provide workload and configuration-aware deterministic performance for microprocessors2019 9,992,299Technologies for network packet cache management2018 9,983,660Providing per core voltage and frequency control2018 9,983,659Providing per core voltage and frequency control2018 9,983,661Providing per core voltage and frequency control2018 9,939,884Providing per core voltage and frequency control2018 9,866,498'Technologies for network packet cache management'2018 9,565,131'Technologies for network packet cache management'2017 9,417,681'Mechanism to provide workload and configuration-aware deterministic performance for microprocessors'2016 9,348,387'Providing per core voltage and frequency control'2016 9,037,840'Mechanism to provide workload and configuration-aware deterministic performance for microprocessors'2015 9,032,226'Providing per core voltage and frequency control'2015 8,943,334'Providing per core voltage and frequency control'2015 8,909,862'Processing out of order transactions for mirrored subsystems using a cache to track write operations'2014 8,533,401'Implementing direct access caches in coherent multiprocessors'2013 8,375,184'Mirroring data between redundant storage controllers of a storage system'2013 7,966,477'Power optimized replay of blocked operations in a pipilined architecture'2011 7,765,349'Apparatus and method for arbitrating heterogeneous agents in on-chip busses'2010 7,757,046'Method and apparatus for optimizing line writes in cache coherent systems'2010 7,725,683'Apparatus and method for power optimized replay via selective recirculation of instructions'2010 7,694,080'Method and apparatus for providing a low power mode for a processor while maintaining snoop throughput'2010 7,640,387'Method and apparatus for implementing heterogeneous interconnects'2009 7,634,603'System and apparatus for early fixed latency subtractive decoding'2009 7,464,208'Method and apparatus for shared resource management in a multiprocessing system'2008 7,464,227'Method and apparatus for supporting opportunistic sharing in coherent multiprocessors'2008 7,428,607'Apparatus and method for arbitrating heterogeneous agents in on-chip busses'2008 7,415,633'Method and apparatus for preventing and recovering from TLB corruption by soft error'2008 7,406,553'System and apparatus for early fixed latency subtractive decoding'2008 7,406,552'Systems and methods for early fixed latency subtractive decoding including speculative acknowledging'2008 7,366,845'Pushing of clean data to one or more processors in a system having a coherency protocol'2008 7,360,007'System including a segmentable, shared bus'2008 7,353,317'Method and apparatus for implementing heterogeneous interconnects'2008 7,219,176'System and apparatus for early fixed latency subtractive decoding'2007 7,216,252'Method and apparatus for machine check abort handling in a multiprocessing system'2007 7,194,671'Mechanism handling race conditions in FRC-enabled processors'2007 7,159,077'Direct processor cache access within a system having a coherent multi-processor protocol'2007 7,143,220'Apparatus and method for granting concurrent ownership to support heterogeneous agents in on-chip busses having different grant-to-valid latencies'2006 7,124,224'Method and apparatus for shared resource management in a multiprocessing system'2006 7,100,001'Methods and apparatus for cache intervention'2006 7,062,613'Methods and apparatus for cache intervention'2006 7,055,060'On-die mechanism for high-reliability processor'2006 7,003,632'Method and apparatus for scalable disambiguated coherence in shared storage hierarchies'2006 6,983,348'Methods and apparatus for cache intervention'2006 6,954,886'Deterministic hardware reset for FRC machine'2005 6,684,346'Method and apparatus for machine check abort handling in a multiprocessing system'2004 6,658,621'System and method for silent data corruption prevention due to next instruction pointer corruption by soft errors'2003 6,651,145'Method and apparatus for scalable disambiguated coherence in shared storage hierarchies'2003 6,615,366'Microprocessor with dual execution core operable in high reliability mode'2003 6,581,688'Method of packing extended reach horizontal wells'2003 6,564,332'Method and apparatus for managing power consumption in a computer system responsive to the power delivery specifications of a power outlet'2003 6,543,028'Silent data corruption prevention due to instruction corruption by soft errors'2003 5,446,612'Self loading suspension for hard disk drives'1995 5,325,921'Method of propagating a hydraulic fracture using fluid loss control particulates'1994 4,755,230'Method of and composition for removing paraffin deposits from hydrocarbon transmission conduits'1988

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1988Based in Houston, TX, US· patent location history

1994–2003Patents assigned to BAKER HUGHES INC (2)· patent assignee history

1994–2003Based in Spring, TX, US· patent location history

1995Based in San Jose, CA, US· patent location history

2003–2020Patents assigned to INTEL CORP (42)· patent assignee history

2003–2020Based in Tempe, AZ, US· patent location history

2007–2011Patents assigned to MARVELL INT LTD (8)· patent assignee history

2013–2015Patents assigned to NGUYEN HANG T (4)· patent assignee history

2013–2015Patents assigned to KUMAR PANKAJ (3)· patent assignee history

2017–2018Based in Tempa, AZ, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	42	2003–2020
MARVELL INT LTD	8	2007–2011
NGUYEN HANG Tself	4	2013–2015
KUMAR PANKAJ	3	2013–2015
BAKER HUGHES INC	2	1994–2003

Locations

Location	Patents	Span
Tempe, AZ, US	48	2003–2020
Tempa, AZ, US	3	2017–2018
Spring, Texas, US	2	1994–2003
San Jose, California, US	1	1995
Houston, Texas, US	1	1988