Inventor
Suddhasattwa NAD
Inventor
US
Overview
Patents· 30 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1030%
H01LSemiconductor devices29%
H05KPrinted circuits14%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h107%
H10DInorganic electric semiconductor devices5%
H01FMagnets4%
H01GCapacitors4%
C08JWorking-up1%
C08LCompositions of macromolecular compounds1%
C23CCoating metallic material1%
PatentTitleYear
12,575,427Defect-free through glass via metallization implementing a sacrificial resist thinning material202612,568,817Surface functionalization of sinx thin film by wet etching for improved adhesion of metal-dielectric for HSIO202612,543,578Electronic packaging architecture with customized variable metal thickness on same buildup layer202612,512,397Substrates having adhesion promotor layers and related methods202512,476,175Glass substrates having transverse capacitors for use with semiconductor packages and related methods202512,412,868Microelectronic assemblies including interconnects with different solder materials202512,349,282Capacitors in through glass vias202512,255,147Electronic substrate having an embedded etch stop to control cavity depth in glass layers therein202512,224,103Angled inductor with small form factor202512,159,825Dielectric-to-metal adhesion promotion material202412,074,102Structural elements for application specific electronic device packages202412,033,930Selectively roughened copper architectures for low insertion loss conductive features202412,027,466Conductive route patterning for electronic substrates202412,002,745High performance integrated RF passives using dual lithography process202411,948,848Subtractive etch resolution implementing a functional thin metal resist202411,942,334Microelectronic assemblies having conductive structures with different thicknesses202411,817,349Conductive route patterning for electronic substrates202311,721,650Method for fabricating multiplexed hollow waveguides of variable type on a semiconductor package202311,694,898Hybrid fine line spacing architecture for bump pitch scaling202311,658,055Customizable release layers to enable low warpage architectures for advanced packaging applications202311,574,993Package architecture with tunable magnetic properties for embedded devices202311,528,811Method, device and system for providing etched metallization structures202211,501,967Selective metal deposition by patterning direct electroless metal plating202211,445,616Interfacial layer for high resolution lithography (HRL) and high speed input/output (IO or I/O) architectures202211,404,389In-situ component fabrication of a highly efficient, high inductance air core inductor integrated into substrate packages202211,291,122Apparatus with a substrate provided with plasma treatment202211,257,748Semiconductor package having polymeric interlayer disposed between conductive elements and dielectric layer202211,227,825High performance integrated RF passives using dual lithography process202211,177,232Circuit device with monolayer bonding between surface structures202111,177,234Package architecture with improved via drill process and method for forming such package2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to INTEL CORP (30)· patent assignee history
2021–2026Based in US· patent location history
2025Patents assigned to THE INTEL CORP (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 30 | 2021–2026 |
| THE INTEL CORP | 1 | 2025 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 30 | 2021–2026 |