Inventor
Susan E. Eisen
Inventor
Round Rock, TX, US
Overview
Patents· 43 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing98%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%
PatentTitleYear
11,119,772Check pointing of accumulator register results in a microprocessor202111,086,630Finish exception handling of an instruction completion table202111,068,274Prioritized instructions in an instruction completion table of a simultaneous multithreading processor202111,068,267High bandwidth logical register flush recovery202111,030,018On-demand multi-tiered hang buster for SMT microprocessor202110,996,995Saving and restoring a transaction memory state202110,977,034Instruction completion table with ready-to-complete vector202110,956,158System and handling of register data in processors202110,949,213Logical register recovery within a processor202110,901,743Speculative execution of both paths of a weakly predicted branch instruction202110,831,489Mechanism for completing atomic instructions in a microprocessor202010,761,856Instruction completion table containing entries that share instruction tags202010,740,140Flush-recovery bandwidth in a processor202010,725,786Completion mechanism for a microprocessor instruction completion table202010,713,057Mechanism to stop completions using stop codes in an instruction completion table202010,664,275Speeding up younger store instruction execution after a sync instruction202010,552,165Efficiently managing speculative finish tracking and error handling for load instructions202010,528,347Executing system call vectored instructions in a multi-slice processor202010,423,423Efficiently managing speculative finish tracking and error handling for load instructions201910,296,339Thread transition management201910,289,415Method and apparatus for execution of threads on processing slices using a history buffer for recording architected register data201910,282,205Method and apparatus for execution of threads on processing slices using a history buffer for restoring architected register data via issued instructions201910,255,071Method and apparatus for managing a speculative transaction in a processing unit201910,073,699Processing instructions in parallel with waw hazards and via a distributed history buffer in a microprocessor having a multi-execution slice architecture201810,067,765Speeding up younger store instruction execution after a sync instruction201810,055,226Thread transition management201810,048,963Executing system call vectored instructions in a multi-slice processor20189,971,687Operation of a multi-slice processor with history buffers storing transaction memory state information20189,703,561'Thread transition management'20179,268,598'Recording and profiling transaction failure source addresses and states of validity indicator corresponding to addresses of aborted transaction in hardware transactional memories'20169,268,599'Recording and profiling transaction failure addresses of the abort-causing and approximate abort-causing data and instructions in hardware transactional memories'20168,725,993'Thread transition management'20148,386,753'Completion arbitration for more than two threads based on resource limitations'20138,261,276'Power-efficient thread priority enablement'20128,131,976'Tracking effective addresses in an out-of-order processor'20127,827,443'Processor instruction retry recovery'20107,467,325'Processor instruction retry recovery'20087,278,011'Completion table configured to track a larger number of outstanding instructions without increasing the size of the completion table'20076,928,533'Data processing system and method for implementing an efficient out-of-order issue mechanism'20056,446,194'Virtual register renamed instruction issue for execution upon virtual/physical rename buffer wrap around detection signaling available physical register'20026,289,437'Data processing system and method for implementing an efficient out-of-order issue mechanism'20016,021,488'Data processing system having an apparatus for tracking a status of an out-of-order operation and method thereof'20005,983,343'Data processing system having an apparatus for de-serialized status register operation and method therefor'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2021Patents assigned to IBM (43)· patent assignee history
1999–2007Based in Austin, TX, US· patent location history
2008–2021Based in Round Rock, TX, US· patent location history
2012–2018Patents assigned to EISEN SUSAN E (5)· patent assignee history
2012–2018Patents assigned to STOLT BENJAMIN W (3)· patent assignee history
2013–2018Patents assigned to NGUYEN DUNG Q (3)· patent assignee history
2014–2018Patents assigned to LE HUNG Q (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 43 | 1999–2021 |
| EISEN SUSAN Eself | 5 | 2012–2018 |
| LE HUNG Q | 3 | 2014–2018 |
| NGUYEN DUNG Q | 3 | 2013–2018 |
| STOLT BENJAMIN W | 3 | 2012–2018 |
Locations
| Location | Patents | Span |
|---|---|---|
| Round Rock, Texas, US | 37 | 2008–2021 |
| Austin, Texas, US | 6 | 1999–2007 |