LexDanaLexDanabeta
Inventor

James S. Dunn

Inventor
Jericho, VT, US

Overview

71→
Patents
1989–2017
Patent span
Electricity
Primary field (CPC H)

Patents· 71 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices40%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1017%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%
H01LSemiconductor devices10%
H01GCapacitors4%
Y10TTechnical subjects covered by former us classification4%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices3%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
G06FElectric digital data processing2%
H01RElectrically-conductive connections1%
PatentTitleYear
9,818,688'Dielectric region in a bulk silicon substrate providing a high-Q passive resonator'20179,653,477'Single-chip field effect transistor (FET) switch with silicon germanium (SiGe) power amplifier and methods of forming'20179,646,993'Single-chip field effect transistor (FET) switch with silicon germanium (SiGe) power amplifier and methods of forming'20179,437,539'Dielectric region in a bulk silicon substrate providing a high-Q passive resonator'20169,424,992'Complimentary metal-insulator-metal (MIM) capacitors and method of manufacture'20169,355,936'Flattened substrate surface for substrate bonding'20169,355,972'Method for making a dielectric region in a bulk silicon substrate providing a high-Q passive resonator'20169,343,589'Field effect transistor (FET) with self-aligned double gates on bulk silicon substrate, methods of forming, and related design structures'20169,337,323'Trench isolation for bipolar junction transistors in BiCMOS technology'20169,269,787'Base profile of self-aligned bipolar transistors for power amplifier applications'20169,257,324'Forming structures on resistive substrates'20169,105,677'Base profile of self-aligned bipolar transistors for power amplifier applications'20158,956,945'Trench isolation for bipolar junction transistors in BiCMOS technology'20158,872,305'Integrated circuit structure having air-gap trench isolation and related design structure'20148,857,022'Method of manufacturing complimentary metal-insulator-metal (MIM) capacitors'20148,842,412'Tapered via and MIM capacitor'20148,778,737'Flattened substrate surface for substrate bonding'20148,735,986'Forming structures on resistive substrates'20148,722,508'Low harmonic RF switch in SOI'20148,692,288'Heterojunction bipolar transistors and methods of manufacture'20148,674,472'Low harmonic RF switch in SOI'20148,649,153'Tapered via and MIM capacitor'20148,633,106'Heterojunction bipolar transistors and methods of manufacture'20148,603,889'Integrated circuit structure having air-gap trench isolation and related design structure'20138,375,539'Method of manufacturing complimentary metal-insulator-metal (MIM) capacitors'20138,237,191'Heterojunction bipolar transistors and methods of manufacture'20128,191,217'Complimentary metal-insulator-metal (MIM) capacitors and method of manufacture'20127,932,155'Structure and method for performance improvement in vertical bipolar transistors'20117,898,061'Structure for performance improvement in vertical bipolar transistors'20117,814,454'Selectable device options for characterizing semiconductor devices'20107,776,704'Method to build self-aligned NPN in advanced BiCMOS technology'20107,713,829'Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology'20107,303,968'Semiconductor device and method having multiple subcollectors formed on a common wafer'20077,265,018'Method to build self-aligned NPN in advanced BiCMOS technology'20077,262,484'Structure and method for performance improvement in vertical bipolar transistors'20077,253,096'Bipolar transistor having raised extrinsic base with selectable self-alignment and methods of forming same'20077,173,274'Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology'20077,135,375'Varactors for CMOS and BiCMOS technologies'20067,064,416'Semiconductor device and method having multiple subcollectors formed on a common wafer'20067,002,221'Bipolar transistor having raised extrinsic base with selectable self-alignment and methods of forming same'20066,906,401'Method to fabricate high-performance NPN transistors in a BiCMOS process'20056,900,519'Diffused extrinsic base and method for fabrication'20056,891,251'Varactors for CMOS and BiCMOS technologies'20056,869,854'Diffused extrinsic base and method for fabrication'20056,833,299'Method of fabricating a stacked poly-poly and MOS capacitor using a sige integration scheme'20046,815,802'Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology'20046,812,545'Epitaxial base bipolar transistor with raised extrinsic base'20046,809,024'Method to fabricate high-performance NPN transistors in a BiCMOS process'20046,683,345'Semiconductor device and method for making the device having an electrically modulated conduction channel'20046,617,220'Method for fabricating an epitaxial base bipolar transistor with raised extrinsic base'20036,597,050'Method of contacting a silicide-based schottky diode and diode so formed'20036,521,506'Varactors for CMOS and BiCMOS technologies'20036,507,063'Poly-poly/MOS capacitor having a gate encapsulating first electrode layer'20036,476,483'Method and apparatus for cooling a silicon on insulator device'20026,448,124'Method for epitaxial bipolar BiCMOS'20026,440,811'Method of fabricating a poly-poly capacitor with a SiGe BiCMOS integration scheme'20026,426,265'Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology'20026,420,766'Transistor having raised source and drain'20026,420,747'MOSCAP design for improved reliability'20026,258,695'Dislocation suppression by carbon incorporation'20016,255,178'Method for forming transistors with raised source and drains and device formed thereby'20016,121,122'Method of contacting a silicide-based schottky diode'20006,100,013'Method for forming transistors with raised source and drains and device formed thereby'20006,096,618'Method of making a Schottky diode with sub-minimum guard ring'20005,981,148'Method for forming sidewall spacers using frequency doubling hybrid resist and device formed thereby'19995,976,768'Method for forming sidewall spacers using frequency doubling hybrid resist and device formed thereby'19995,882,977'Method of forming a self-aligned, sub-minimum isolation ring'19995,705,407'Method of forming high performance bipolar devices with improved wiring options'19985,631,495'High performance bipolar devices with plurality of base contact regions formed around the emitter layer'19974,891,020'Low profile metal shell electrical connector'19904,820,188'Metal shell electrical connector and subassembly therefor'1989

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1989–1990Based in Doylestown, PA, US· patent location history
1997–2017Patents assigned to IBM (65)· patent assignee history
1997–2017Based in Jericho, VT, US· patent location history
2012–2016Patents assigned to DUNN JAMES S (10)· patent assignee history
2012–2016Patents assigned to STAMPER ANTHONY K (8)· patent assignee history
2012–2016Patents assigned to HE ZHONG-XIANG (5)· patent assignee history
2016Patents assigned to GLOBALFOUNDRIES INC (5)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
IBM651997–2017
DUNN JAMES Sself102012–2016
STAMPER ANTHONY K82012–2016
GLOBALFOUNDRIES INC52016
HE ZHONG-XIANG52012–2016
Locations
LocationPatentsSpan
Jericho, VT, US691997–2017
Doylestown, Pennsylvania, US21989–1990