Inventor
Larry A. Nesbit
Inventor
Williston, VT, US
Overview
Patents· 49 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1021%
H10DInorganic electric semiconductor devices16%
H10BElectronic memory devices14%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests11%
B82YSpecific uses or applications of nanostructures7%
H10KOrganic electric solid-state devices5%
C01BNon-metallic elements2%
B82BNanostructures formed by manipulation of individual atoms, molecules, or limited collections of atoms or molecules as discrete units2%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices2%
PatentTitleYear
7,994,575'Metal-oxide-semiconductor device structures with tailored dopant depth profiles'20117,951,660'Methods for fabricating a metal-oxide-semiconductor device structure'20117,932,549'Carbon nanotube conductor for trench capacitors'20117,851,064'Methods and structures for promoting stable synthesis of carbon nanotubes'20107,829,883'Vertical carbon nanotube field effect transistors and arrays'20107,820,502'Methods of fabricating vertical carbon nanotube field effect transistors for arrangement in arrays and field effect transistors and arrays formed thereby'20107,691,720'Vertical nanotube semiconductor device structures and methods of forming the same'20107,585,614'Sub-lithographic imaging techniques and processes'20097,525,156'Shallow trench isolation fill by liquid phase deposition of SiO2'20097,504,314'Method for fabricating oxygen-implanted silicon on insulation type semiconductor and semiconductor formed therefrom'20097,393,779'Shrinking contact apertures through LPD oxide'20087,374,793'Methods and structures for promoting stable synthesis of carbon nanotubes'20087,329,567'Vertical field effect transistors incorporating semiconducting nanotubes grown in a spacer-defined passage'20087,273,794'Shallow trench isolation fill by liquid phase deposition of SiO2'20077,264,415'Methods of forming alternating phase shift masks having improved phase-shift tolerance'20077,256,114'Process for oxide cap formation in semiconductor manufacturing'20077,250,347'Double-gate FETs (Field Effect Transistors)'20077,244,980'Line mask defined active areas for 8F2 DRAM cells with folded bit lines and deep trench patterns'20077,211,844'Vertical field effect transistors incorporating semiconducting nanotubes grown in a spacer-defined passage'20077,187,085'Semiconductor device including dual damascene interconnections'20077,125,790'Inclusion of low-k dielectric material between bit lines'20067,038,299'Selective synthesis of semiconducting carbon nanotubes'20066,998,204'Alternating phase mask built by additive film deposition'20066,989,308'Method of forming FinFET gates without long etches'20066,890,815'Reduced cap layer erosion for borderless contacts'20056,890,828'Method for supporting a bond pad in a multilevel interconnect structure and support structure formed thereby'20056,875,685'Method of forming gas dielectric with support structure'20056,790,739'Structure and methods for process integration in vertical DRAM cell fabrication'20046,767,781'Structure and method of forming bitline contacts for a vertical DRAM array using a line bitline contact mask'20046,759,332'Method for producing dual damascene interconnections and structure produced thereby'20046,727,539'Embedded vertical DRAM arrays with silicided bitline and polysilicon interconnect'20046,713,835'Method for manufacturing a multi-level interconnect structure'20046,686,668'Structure and method of forming bitline contacts for a vertical DRAM array using a line bitline contact mask'20046,620,676'Structure and methods for process integration in vertical DRAM cell fabrication'20036,573,137'Single sided buried strap'20036,541,810'Modified vertical MOSFET and methods of formation thereof'20036,509,624'Semiconductor fuses and antifuses in vertical DRAMS'20036,429,068'Structure and method of fabricating embedded vertical DRAM arrays with silicided bitline and polysilicon interconnect'20026,309,924'Method of forming self-limiting polysilicon LOCOS for DRAM cell'20016,245,651'Method of simultaneously forming a line interconnect and a borderless contact to diffusion'20016,184,107'Capacitor trench-top dielectric for self-aligned device isolation'20016,084,276'Threshold voltage tailoring of corner of MOSFET device'20005,994,202'Threshold voltage tailoring of the corner of a MOSFET device'19995,923,991'Methods to prevent divot formation in shallow trench isolation areas'19994,601,779'Method of producing a thin silicon-on-insulator layer'19864,558,508'Process of making dual well CMOS semiconductor structure with aligned field-dopings using single masking step'19854,532,700'Method of manufacturing semiconductor structures having an oxidized porous silicon isolation layer'19854,398,341'Method of fabricating a highly conductive structure'19834,389,257'Fabrication method for high conductivity, void-free polysilicon-silicide integrated circuit electrodes'1983Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1983–2011Patents assigned to IBM (48)· patent assignee history
1983–2011Based in Williston, VT, US· patent location history
1999–2004Based in Farmington, CT, US· patent location history
2001Patents assigned to SIEMENS MICROELECTRONICS (1)· patent assignee history
2002–2004Patents assigned to INFINEON TECHNOLOGIES CORP (4)· patent assignee history
2003–2006Patents assigned to INFINEON TECHNOLOGIES AG (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 48 | 1983–2011 |
| INFINEON TECHNOLOGIES CORP | 4 | 2002–2004 |
| INFINEON TECHNOLOGIES AG | 2 | 2003–2006 |
| SIEMENS MICROELECTRONICS | 1 | 2001 |
Locations
| Location | Patents | Span |
|---|---|---|
| Williston, VT, US | 40 | 1983–2011 |
| Farmington, CT, US | 9 | 1999–2004 |