Inventor
Bo-Wei Hsieh
Inventor
Tainan, TW
Overview
Patents· 21 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores42%
G06FElectric digital data processing29%
H03KPulse technique9%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses4%
H04LTransmission of digital information, e.g. telegraphic communication4%
B60WConjoint control of vehicle sub-units of different type or different function2%
G10HElectrophonic musical instruments2%
G10LSpeech analysis techniques or speech synthesis2%
H03MCoding2%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%
PatentTitleYear
11,017,839DRAM, memory controller and associated training method202110,964,363Delay tracking method and memory system202110,878,879Refresh control method for memory system to perform refresh action on all memory banks of the memory system within refresh window202010,846,018Memory device, memory controller and associated memory system operated according to selected clock signals202010,810,078Method of parity training for a DRAM supporting a link error checking and correcting functionality202010,163,485Memory module, memory controller and associated control method for read training technique201810,141,044Memory interface circuit having signal detector for detecting clock signal201810,109,341Memory capable of entering/exiting power down state during self-refresh period and associated memory controller and memory system201810,083,728Memory controller, memory module and memory system201810,008,255DRAM and access and operating method thereof20189,871,518'Memory interface circuit capable of controlling driving ability and associated control method'20189,829,914Method for performing signal control of an electronic device, and associated apparatus20179,824,728'Method for performing memory interface calibration in an electronic device, and associated apparatus and associated memory controller'20179,812,187'Termination topology of memory system and associated memory module and control method'20179,792,975'Dram and access and operating method thereof'20179,613,665'Method for performing memory interface control of an electronic device, and associated apparatus'20178,952,718'Termination circuit and DC balance method thereof'20157,573,759'Method for detecting data strobe signal'20097,552,292'Method of memory space configuration'20097,382,665'Method for detecting data strobe signal'20087,257,035'Method for detecting data strobe signal'2007Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2007–2009Patents assigned to VIA TECH INC (4)· patent assignee history
2007–2009Based in Hsin-Tien, TW· patent location history
2008–2009Based in Taipei, TW· patent location history
2015–2021Patents assigned to MEDIATEK INC (17)· patent assignee history
2015Patents assigned to CHANG SHENG-MING (1)· patent assignee history
2015Patents assigned to CHEN SHANG-PING (1)· patent assignee history
2015Patents assigned to HSIEH BO-WEI (1)· patent assignee history
2015–2018Based in Tainan, TW· patent location history
2017–2021Based in Hsinchu, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MEDIATEK INC | 17 | 2015–2021 |
| VIA TECH INC | 4 | 2007–2009 |
| CHANG SHENG-MING | 1 | 2015 |
| CHEN SHANG-PING | 1 | 2015 |
| HSIEH BO-WEIself | 1 | 2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Tainan, TW | 10 | 2015–2018 |
| Hsinchu, TW | 7 | 2017–2021 |
| Taipei, TW | 2 | 2008–2009 |
| Hsin-Tien, TW | 2 | 2007–2009 |