Inventor
Qiuling Zhu
Inventor
San Jose, CA, US
Overview
Patents· 27 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Tprimary
G06TImage data processing or generation, in general36%
H04NPictorial communication, e.g. television29%
G06FElectric digital data processing19%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use8%
B41FPrinting machines or presses4%
G09GArrangements or circuits for control of indicating devices using static means to present variable information3%
H04LTransmission of digital information, e.g. telegraphic communication1%
PatentTitleYear
10,872,393Image processor with high throughput internal communication protocol202010,791,284Virtual linebuffers for image signal processors202010,754,654Energy efficient processor core architecture for image processor202010,719,905Architecture for high performance, power efficient, programmable image processing202010,685,422Compiler managed memory for image processor202010,685,423Determination of per line buffer unit memory allocation202010,638,073Line buffer unit for image processor202010,560,598Sheet generator for image processor202010,516,833Virtual linebuffers for image signal processors201910,430,919Determination of per line buffer unit memory allocation201910,417,732Architecture for high performance, power efficient, programmable image processing201910,397,450Two dimensional shift array for image processor201910,321,077Line buffer unit for image processor201910,304,156Compiler managed memory for image processor201910,291,813Sheet generator for image processor201910,284,744Sheet generator for image processor201910,275,253Energy efficient processor core architecture for image processor201910,277,833Virtual linebuffers for image signal processors201910,216,487Virtual image processor instruction set architecture (ISA) and memory model and exemplary target hardware having a two-dimensional shift array structure201910,204,396Compiler managed memory for image processor201910,095,479Virtual image processor instruction set architecture (ISA) and memory model and exemplary target hardware having a two-dimensional shift array structure20189,965,824Architecture for high performance, power efficient, programmable image processing20189,772,852'Energy efficient processor core architecture for image processor'20179,769,356'Two dimensional shift array for image processor'20179,756,268'Line buffer unit for image processor'20179,749,548'Virtual linebuffers for image signal processors'20179,286,216'3DIC memory chips including computational logic-in-memory for performing accelerated data processing'2016Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2016Patents assigned to UNIV CARNEGIE MELLON (1)· patent assignee history
2016–2020Based in San Jose, CA, US· patent location history
2017Patents assigned to GOOGLE INC (4)· patent assignee history
2018–2020Patents assigned to GOOGLE LLC (22)· patent assignee history
2019–2020Based in Santa Clara, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| GOOGLE LLC | 22 | 2018–2020 |
| GOOGLE INC | 4 | 2017 |
| UNIV CARNEGIE MELLON | 1 | 2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 25 | 2016–2020 |
| Santa Clara, California, US | 2 | 2019–2020 |