Inventor
Paul M. Solomon
Inventor
Yorktown Heights, NY, US
Overview
Patents· 120 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices29%
H01LSemiconductor devices13%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h106%
H10BElectronic memory devices6%
G11CStatic stores5%
B82YSpecific uses or applications of nanostructures4%
H10NElectric solid-state devices not otherwise provided for3%
G06NComputing arrangements based on specific computational models3%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation2%
PatentTitleYear
11,121,316Symmetric tunable PCM resistor for artificial intelligence circuits202111,107,835BEOL cross-bar array ferroelectric synapse units for domain wall movement202111,101,219Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elements202111,094,820Mobile ferroelectric single domain wall implementation of a symmetric resistive processing unit202111,055,611Circuit for CMOS based resistive processing unit202111,055,610Circuit for CMOS based resistive processing unit202111,054,306Self-clocked low noise photoreceiver (SCLNP)202111,011,387Wet etching of samarium selenium for piezoelectric processing202110,985,105Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elements202110,964,881Piezoelectronic device with novel force amplification202110,950,304Circuit methodology for highly linear and symmetric resistive processing unit202110,930,519Wet etching of samarium selenium for piezoelectric processing202110,928,356Ion sensitive field effect transistor (FET) with back-gate coupled reference electrode202110,896,979Compact vertical injection punch through floating gate analog memory and a manufacture thereof202110,804,261Indirect readout FET202010,777,645P-N junction based devices with single species impurity for P-type and N-type doping202010,755,759Symmetrically programmable resistive synapse for RPU using current-programmed single domain wall ferroelectric202010,707,148Elbow contact for field-effect transistor and manufacture thereof202010,680,105Mobile ferroelectric single domain wall implementation of a symmetric resistive processing unit202010,658,384Ferro-electric complementary FET202010,615,261P-N junction based devices with single species impurity for P-type and N-type doping202010,615,176Ferro-electric complementary FET202010,586,922Symmetric tunable PCM resistor for artificial intelligence circuits202010,586,849Field effect transistor with controllable resistance202010,571,331Self-clocked low noise photoreceiver (SCLNP)202010,559,562Indirect readout FET202010,541,191Elbow contact for field-effect transistor and manufacture thereof202010,468,432BEOL cross-bar array ferroelectric synapse units for domain wall movement201910,411,101P-N junction based devices with single species impurity for P-type and N-type doping201910,374,041Field effect transistor with controllable resistance201910,374,163Intermetallic contact for carbon nanotube FETs201910,354,824Piezoelectronic switch device for RF applications201910,332,874Indirect readout FET201910,332,753Wet etching of samarium selenium for piezoelectric processing201910,319,439Resistive processing unit weight reading via collection of differential current from first and second memory elements201910,269,714Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elements201910,269,580Wet etching of samarium selenium for piezoelectric processing201910,269,425Circuit methodology for highly linear and symmetric resistive processing unit201910,242,991Highly compact floating gate analog memory201910,204,907Metal-insulator-metal capacitor analog memory unit cell201910,170,702Intermetallic contact for carbon nanotube FETs201910,134,472Floating gate architecture for deep neural network application201810,079,234Metal-insulator-metal capacitor analog memory unit cell20189,941,472Piezoelectronic device with novel force amplification20189,915,561'Self-clocked low noise photoreceiver (SCLNP)'20189,881,759'Piezoelectronic switch device for RF applications'20189,852,790Circuit methodology for highly linear and symmetric resistive processing unit20179,472,368'Piezoelectronic switch device for RF applications'20169,105,571'Interface engineering to optimize metal-III-V contacts'20159,099,327'Multigate structure formed with electroless metal deposition'20159,058,868'Piezoelectronic memory'20158,936,978'Multigate structure formed with electroless metal deposition'20158,796,735'Fabrication of a vertical heterojunction tunnel-FET'20148,785,995'Ferroelectric semiconductor transistor devices having gate modulated conductive layer'20148,741,753'Use of band edge gate metals as source drain contacts'20148,741,756'Contacts-first self-aligned carbon nanotube transistor with gate-all-around'20148,674,412'Contacts-first self-aligned carbon nanotube transistor with gate-all-around'20148,664,721'FET with FUSI gate and reduced source/drain contact resistance'20148,614,436'Solid state klystron'20138,557,665'Self-aligned metal-semiconductor alloy and metallization for sub-lithographic source and drain contacts'20138,455,311'Solid state klystron'20138,288,803'Tunnel field effect devices'20128,283,703'Solid state Klystron'20128,258,031'Fabrication of a vertical heterojunction tunnel-FET'20128,153,494'Nanowire MOSFET with doped epitaxial contacts for source and drain'20127,999,251'Nanowire MOSFET with doped epitaxial contacts for source and drain'20117,943,486'Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain'20117,888,742'Self-aligned metal-semiconductor alloy and metallization for sub-lithographic source and drain contacts'20117,749,905'Vertical Fet with nanowire channels and a silicided bottom contact'20107,723,196'Damascene gate field effect transistor with an internal spacer structure'20107,648,880'Nitride-encapsulated FET (NNCFET)'20107,627,840'Method for soft error modeling with double current pulse'20097,498,640'Self-aligned silicide process for silicon sidewall source and drain contacts and structure formed thereby'20097,479,684'Field effect transistor including damascene gate with an internal spacer structure'20097,462,525'Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain'20087,459,752'Ultra thin body fully-depleted SOI MOSFETs'20087,446,025'Method of forming vertical FET with nanowire channels and a silicided bottom contact'20087,442,612'Nitride-encapsulated FET (NNCFET)'20087,314,790'Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain'20087,259,049'Self-aligned isolation double-gate FET'20077,253,431'Method and apparatus for solution processed doping of carbon nanotube'20077,230,286'Vertical FET with nanowire channels and a silicided bottom contact'20077,161,169'Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain'20077,145,212'Method for manufacturing device substrate with metal back-gate and structure formed thereby'20067,091,069'Ultra thin body fully-depleted SOI MOSFETs'20067,078,773'Nitride-encapsulated FET (NNCFET)'20066,987,050'Self-aligned silicide (salicide) process for low resistivity contacts to thin film silicon-on-insulator and bulk MOSFETS and for shallow junctions'20066,946,696'Self-aligned isolation double-gate FET'20056,864,520'Germanium field effect transistor and method of fabricating the same'20056,803,266'Process for passivating the semiconductor-dielectric interface of a MOS device and MOS device formed thereby'20046,797,604'Method for manufacturing device substrate with metal back-gate and structure formed thereby'20046,762,101'Damascene double-gate FET'20046,716,708'Self-aligned silicide process utilizing ion implants for reduced silicon consumption and control of the silicide formation temperature and structure formed thereby'20046,645,861'Self-aligned silicide process for silicon sidewall source and drain contacts'20036,603,181'MOS device having a passivated semiconductor-dielectric interface'20036,579,614'Structure having refractory metal film on a substrate'20036,580,132'Damascene double-gate FET'20036,555,880'Self-aligned silicide process utilizing ion implants for reduced silicon consumption and control of the silicide formation temperature and structure formed thereby'20036,444,578'Self-aligned silicide process for reduction of Si consumption in shallow junction and thin SOI electronic devices'20026,437,422'Active devices using threads'20026,339,002'Method utilizing CMP to fabricate double gate MOSFETS with conductive sidewall contacts'20026,333,247'Two-step MOSFET gate formation for high-density devices'20016,281,551'Back-plane for semiconductor device'20016,238,737'Method for protecting refractory metal thin film requiring high temperature processing in an oxidizing atmosphere and structure formed thereby'20016,057,212'Method for making bonded metal back-plane substrates'20006,005,415'Switching circuit for large voltages'19995,960,265'Method of making EEPROM having coplanar on-insulator FET and control gate'19995,886,376'EEPROM having coplanar on-insulator FET and control gate'19995,773,331'Method for making single and double gate field effect transistors with sidewall source-drain contacts'19985,506,520'Energy conserving clock pulse generating circuits'19965,471,948'Method of making a compound semiconductor having metallic inclusions'19955,371,399'Compound semiconductor having metallic inclusions and devices fabricated therefrom'19945,019,882'Germanium channel silicon MOSFET'19914,965,645'Saturable charge FET'19904,962,409'Staggered bandgap gate field effect transistor'19904,910,562'Field induced base transistor'19904,866,491'Heterojunction field effect transistor having gate threshold voltage capability'19894,616,242'Enhancement and depletion mode selection layer for field effect transistor'19864,483,726'Double self-aligned fabrication process for making a bipolar transistor structure having a small polysilicon-to-extrinsic base contact area'19844,458,162'TTL Logic gate'1984Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1984–2021Patents assigned to IBM (120)· patent assignee history
1984–2021Based in Yorktown Heights, NY, US· patent location history
2004Based in Yorktown, NY, US· patent location history
2012–2015Patents assigned to SOLOMON PAUL M (14)· patent assignee history
2014–2015Patents assigned to LAVOIE CHRISTIAN (5)· patent assignee history
2014–2015Patents assigned to ZHANG ZHEN (5)· patent assignee history
2014–2015Patents assigned to YANG BIN (3)· patent assignee history
2017–2021Based in Ossining, NY, US· patent location history
2018–2021Based in Westchester, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 120 | 1984–2021 |
| SOLOMON PAUL Mself | 14 | 2012–2015 |
| LAVOIE CHRISTIAN | 5 | 2014–2015 |
| ZHANG ZHEN | 5 | 2014–2015 |
| YANG BIN | 3 | 2014–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Yorktown Heights, New York, US | 103 | 1984–2021 |
| Westchester, New York, US | 13 | 2018–2021 |
| Ossining, New York, US | 3 | 2017–2021 |
| Yorktown, New York, US | 1 | 2004 |