Inventor
Thurman J. Rodgers
Inventor
Woodside, CA, US
Overview
Patents· 18 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1021%
H10DInorganic electric semiconductor devices15%
G11CStatic stores13%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1013%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests13%
H03KPulse technique5%
H10BElectronic memory devices5%
B81BMicrostructural devices or systems, e.g. micromechanical devices3%
G01RMeasuring electric variables3%
G06FElectric digital data processing3%
PatentTitleYear
9,624,094'Hydrogen barriers in a copper interconnect process'20178,106,637'Programmable floating gate reference'20127,660,086'Programmable electrostatic discharge (ESD) protection device'20107,507,944'Non-planar packaging of image sensor'20097,227,212'Method of forming a floating metal structure in an integrated circuit'20077,227,804'Current source architecture for memory device standby current reduction'20077,045,387'Method of performing back-end manufacturing of an integrated circuit device'20066,903,002'Low-k dielectric layer with air gaps'20056,847,218'Probe card with an adapter layer for testing integrated circuits'20056,835,616'Method of forming a floating metal structure in an integrated circuit'20046,730,545'Method of performing back-end manufacturing of an integrated circuit device'20046,185,126'Self-initializing RAM-based programmable device'20016,131,140'Integrated cache memory with system control logic and adaptation of RAM bus to a cache pinout'20005,977,638'Edge metal for interconnect layers'19994,764,248'Rapid thermal nitridized oxide locos process'19884,222,063'VMOS Floating gate memory with breakdown voltage lowering region'19804,222,062'VMOS Floating gate memory device'19803,975,221'Low capacitance V groove MOS NOR gate and method of manufacture'1976Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1976–1980Patents assigned to AMERICAN MICRO SYST (3)· patent assignee history
1976–1980Based in Palo Alto, CA, US· patent location history
1980Based in Menlo Park, CA, US· patent location history
1988–2017Patents assigned to CYPRESS SEMICONDUCTOR CORP (15)· patent assignee history
1988–2017Based in Woodside, CA, US· patent location history
2012Patents assigned to KUTZ HAROLD (1)· patent assignee history
2012Patents assigned to RODGERS THURMAN J (1)· patent assignee history
2012Patents assigned to SNYDER WARREN (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| CYPRESS SEMICONDUCTOR CORP | 15 | 1988–2017 |
| AMERICAN MICRO SYST | 3 | 1976–1980 |
| KUTZ HAROLD | 1 | 2012 |
| RODGERS THURMAN Jself | 1 | 2012 |
| SNYDER WARREN | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Woodside, California, US | 15 | 1988–2017 |
| Palo Alto, California, US | 2 | 1976–1980 |
| Menlo Park, California, US | 1 | 1980 |