Inventor
Dong-Hyeon Jang
Inventor
Suwon-si, KR
Overview
Patents· 42 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1048%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h109%
H01LSemiconductor devices6%
H05KPrinted circuits5%
Y02PClimate change mitigation technologies in the production or processing of goods5%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%
Y10TTechnical subjects covered by former us classification5%
A47GHousehold or table equipment2%
G11CStatic stores2%
H04NPictorial communication, e.g. television2%
PatentTitleYear
11,119,601Screen output method using external device and electronic device for supporting the same202110,438,899Semiconductor packages20199,941,196Semiconductor device, fabricating method thereof and semiconductor package including the semiconductor device20189,343,361'Semiconductor device, fabricating method thereof and semiconductor package including the semiconductor device'20169,245,827'3D semiconductor device'20169,136,260'Method of manufacturing chip-stacked semiconductor package'20158,743,582'3D semiconductor device'20148,735,276'Semiconductor packages and methods of manufacturing the same'20148,637,969'Stacked chips in a semiconductor package'20148,637,350'Method of manufacturing chip-stacked semiconductor package'20148,592,991'Semiconductor device, fabricating method thereof and semiconductor package including the semiconductor device'20138,455,301'Method of fabricating stacked chips in a semiconductor package'20138,368,231'Chipstack package and manufacturing method thereof'20138,362,621'Microelectronic devices including multiple through-silicon via structures on a conductive pad and methods of fabricating the same'20138,119,448'Semiconductor chip, wafer stack package using the same, and methods of manufacturing the same'20128,110,922'Wafer level semiconductor module and method for manufacturing the same'20127,977,156'Chipstack package and manufacturing method thereof'20117,923,296'Board on chip package and method of manufacturing the same'20117,855,144'Method of forming metal lines and bumps for semiconductor devices'20107,825,495'Semiconductor chip structure, method of manufacturing the semiconductor chip structure, semiconductor chip package, and method of manufacturing the semiconductor chip package'20107,598,607'Semiconductor packages with enhanced joint reliability and methods of fabricating the same'20097,592,709'Board on chip package and method of manufacturing the same'20097,545,027'Wafer level package having redistribution interconnection layer and method of forming the same'20097,537,959'Chip stack package and manufacturing method thereof'20097,534,656'Image sensor device and method of manufacturing the same'20097,312,143'Wafer level chip scale package having a gap and method for manufacturing the same'20077,307,340'Wafer-level electronic modules with integral connector contacts'20077,300,864'Method for forming solder bump structure'20077,276,799'Chip stack package and manufacturing method thereof'20077,274,097'Semiconductor package including redistribution pattern and method of manufacturing the same'20077,262,475'Image sensor device and method of manufacturing same'20077,224,055'Center pad type IC chip with jumpers, method of processing the same and multi chip package'20077,205,660'Wafer level chip scale package having a gap and method for manufacturing the same'20077,196,000'Method for manufacturing a wafer level chip scale package'20076,903,451'Chip scale packages manufactured at wafer level'20056,836,018'Wafer level package and method for manufacturing the same'20046,607,938'Wafer level stack chip package and method for manufacturing same'20036,586,275'Wafer level package and method for manufacturing the same'20036,555,921'Semiconductor package'20036,518,675'Wafer level package and method for manufacturing the same'20036,376,279'method for manufacturing a semiconductor package'20026,187,615'Chip scale packages and methods for manufacturing the chip scale packages at wafer level'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2021Patents assigned to SAMSUNG ELECTRONICS CO LTD (42)· patent assignee history
2001–2007Based in Seoul, KR· patent location history
2003–2004Based in Kyungki-do, KR· patent location history
2007–2014Based in Suwon-si, KR· patent location history
2007–2021Based in Gyeonggi-do, KR· patent location history
2012–2014Patents assigned to JANG DONG-HYEON (9)· patent assignee history
2012–2014Patents assigned to BAEK SEUNG-DUK (3)· patent assignee history
2012–2019Based in Yongin-si, KR· patent location history
2013–2014Patents assigned to SONG HO-GEON (4)· patent assignee history
2013–2014Patents assigned to IM SUNG-JUN (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SAMSUNG ELECTRONICS CO LTD | 42 | 2001–2021 |
| JANG DONG-HYEONself | 9 | 2012–2014 |
| SONG HO-GEON | 4 | 2013–2014 |
| BAEK SEUNG-DUK | 3 | 2012–2014 |
| IM SUNG-JUN | 3 | 2013–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Suwon-si, KR | 17 | 2007–2014 |
| Yongin-si, KR | 10 | 2012–2019 |
| Seoul, KR | 7 | 2001–2007 |
| Gyeonggi-do, KR | 5 | 2007–2021 |
| Kyungki-do, KR | 3 | 2003–2004 |