Inventor
Maitreyee Mahajani
Inventor
Saratoga, CA, US
Overview
Patents· 46 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices24%
C23CCoating metallic material14%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1013%
H10BElectronic memory devices12%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1011%
G11CStatic stores11%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation7%
H01LSemiconductor devices3%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
H01JElectric discharge tubes or discharge lamps2%
PatentTitleYear
9,269,584'N-metal film deposition with initiation layer'20169,048,183'NMOS metal gate materials, manufacturing methods, and equipment using CVD and ALD processes with metal based precursors'20158,987,080'Methods for manufacturing metal gates'20158,951,861'Methods of making a high-density nonvolatile memory'20158,895,443'N-metal film deposition with initiation layer'20148,778,816'In situ vapor phase surface activation of SiO2 '20148,642,468'NMOS metal gate materials, manufacturing methods, and equipment using CVD and ALD processes with metal based precursors'20148,633,119'Methods for manufacturing high dielectric constant films'20148,633,114'Methods for manufacturing high dielectric constant films'20148,592,305'Doping aluminum in tantalum silicide'20138,383,478'High-density nonvolatile memory and methods of making the same'20138,361,910'Pretreatment processes within a batch ALD reactor'20138,043,907'Atomic layer deposition processes for non-volatile memory devices'20118,004,033'High-density nonvolatile memory'20117,972,978'Pretreatment processes within a batch ALD reactor'20117,921,803'Chamber components with increased pyrometry visibility'20117,915,164'Method for forming doped polysilicon via connecting polysilicon layers'20117,915,163'Method for forming doped polysilicon via connecting polysilicon layers'20117,897,208'Low temperature ALD SiO2 '20117,798,096'Plasma, UV and ion/neutral assisted ALD or CVD in a batch tool'20107,776,395'Method of depositing catalyst assisted silicates of high-k materials'20107,749,574'Low temperature ALD SiO2'20107,659,158'Atomic layer deposition processes for non-volatile memory devices'20107,572,052'Method for monitoring and calibrating temperature in semiconductor processing chambers'20097,566,974'Doped polysilicon via connecting polysilicon layers'20097,557,405'High-density nonvolatile memory'20097,508,714'Memory array incorporating mirrored NAND strings and non-shared global bit lines within a block'20097,495,337'Dual-gate device and method'20097,462,521'Dual-gate device and method'20087,402,534'Pretreatment processes within a batch ALD reactor'20087,221,588'Memory array incorporating memory cells arranged in NAND strings'20077,026,212'Method for making high density nonvolatile memory'20067,012,299'Storage layer optimization of a nonvolatile memory device'20067,009,275'Method for making high density nonvolatile memory'20066,995,422'High-density three-dimensional memory'20066,984,561'Method for making high density nonvolatile memory'20066,960,794'Formation of thin channels for TFT devices to ensure low variability of threshold voltages'20056,952,030'High-density three-dimensional memory cell'20056,858,899'Thin film transistor with metal oxide layer and method of making same'20056,464,795'Substrate support member for a processing chamber'20026,328,808'Apparatus and method for aligning and controlling edge deposition on a substrate'20016,271,129'Method for forming a gap filling refractory metal layer having reduced stress'20016,186,092'Apparatus and method for aligning and controlling edge deposition on a substrate'20016,174,373'Non-plasma halogenated gas flow prevent metal residues'20016,070,599'Non-plasma halogenated gas flow to prevent metal residues'20005,709,772'Non-plasma halogenated gas flow to prevent metal residues'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2016Patents assigned to APPLIED MATERIALS INC (27)· patent assignee history
1998–2001Based in Santa Clara, CA, US· patent location history
2001–2002Based in San Jose, CA, US· patent location history
2001Based in Sunnyvale, CA, US· patent location history
2005–2006Patents assigned to MATRIX SEMICONDUCTOR INC (6)· patent assignee history
2005–2016Based in Saratoga, CA, US· patent location history
2007–2015Patents assigned to SANDISK 3D LLC (9)· patent assignee history
2008–2016Patents assigned to MAHAJANI MAITREYEE (11)· patent assignee history
2013–2016Patents assigned to CHANG MEI (4)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| APPLIED MATERIALS INC | 27 | 1998–2016 |
| MAHAJANI MAITREYEEself | 11 | 2008–2016 |
| SANDISK 3D LLC | 9 | 2007–2015 |
| MATRIX SEMICONDUCTOR INC | 6 | 2005–2006 |
| CHANG MEI | 4 | 2013–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Saratoga, California, US | 39 | 2005–2016 |
| Santa Clara, California, US | 3 | 1998–2001 |
| San Jose, California, US | 2 | 2001–2002 |
| Sunnyvale, California, US | 2 | 2001 |