Inventor
Eric Lee
Inventor
San Jose, CA, US
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores39%
G06FElectric digital data processing24%
H01LSemiconductor devices8%
H03KPulse technique8%
H10BElectronic memory devices5%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%
G01RMeasuring electric variables3%
H03MCoding3%
H04LTransmission of digital information, e.g. telegraphic communication3%
H10DInorganic electric semiconductor devices3%
PatentTitleYear
10,802,721Memory devices configured to latch data for output in response to an edge of a clock signal generated in response to an edge of another clock signal202010,741,252Apparatus and methods for programming memory cells using multi-step programming pulses202010,719,313Providing external access to a processing platform202010,650,895Memory devices with distributed block select for a vertical string driver tile architecture202010,580,791Semiconductor device structures, semiconductor devices, and electronic systems202010,453,533Memory devices with distributed block select for a vertical string driver tile architecture201910,387,048Memory devices configured to latch data for output in response to an edge of a clock signal generated in response to an edge of another clock signal201910,373,970Semiconductor device structures including staircase structures, and related methods and electronic systems201910,360,956Wave pipeline201910,019,170Controlling timing and edge transition of a delayed clock signal and data latching methods using such a delayed clock signal20189,710,182'Apparatuses and methods for a memory die architecture including an interface memory'20179,478,270'Data paths using a first signal to capture data and a second signal to output data and methods for providing data'20169,460,803'Data path with clock-data tracking'20169,190,133'Apparatuses and methods for a memory die architecture including an interface memory'20159,183,900'Data paths using a first signal to capture data and a second signal to output data and methods for providing data'20158,977,917'Highly secure and extensive scan testing of integrated circuits'20158,937,839'Data paths using a first signal to capture data and a second signal to output data and methods for providing data'20158,368,424'Programmable logic device wakeup using a general purpose input/output port'20138,319,521'Safe programming of key information into non-volatile memory for a programmable logic device'2012Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2012–2015Patents assigned to LATTICE SEMICONDUCTOR CORP (3)· patent assignee history
2012–2013Patents assigned to CHEN ZHENG (2)· patent assignee history
2012–2013Patents assigned to HAN WEI (2)· patent assignee history
2012–2013Patents assigned to JUENEMANN WARREN (2)· patent assignee history
2012Based in Hillsboro, OR, US· patent location history
2013–2015Based in Allentown, PA, US· patent location history
2015–2020Patents assigned to MICRON TECHNOLOGY INC (15)· patent assignee history
2015–2020Based in San Jose, CA, US· patent location history
2015Based in Santa Clara, CA, US· patent location history
2020Based in Washington, DC, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 15 | 2015–2020 |
| LATTICE SEMICONDUCTOR CORP | 3 | 2012–2015 |
| CHEN ZHENG | 2 | 2012–2013 |
| HAN WEI | 2 | 2012–2013 |
| JUENEMANN WARREN | 2 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 14 | 2015–2020 |
| Allentown, Pennsylvania, US | 2 | 2013–2015 |
| Washington, DC, US | 1 | 2020 |
| Santa Clara, California, US | 1 | 2015 |
| Hillsboro, OR, US | 1 | 2012 |