LexDanaLexDanabeta
Inventor

Fu-Chang Hsu

Inventor
San Jose, CA, US

Overview

117→
Patents
1997–2020
Patent span
Physics
Primary field (CPC G)

Patents· 117 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores48%
H10BElectronic memory devices26%
H10DInorganic electric semiconductor devices9%
H01LSemiconductor devices6%
G06FElectric digital data processing3%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%
G05FSystems for regulating electric or magnetic variables1%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems1%
H10NElectric solid-state devices not otherwise provided for1%
H03KPulse technique1%
PatentTitleYear
10,840,3013D vertical memory array cell structures with individual selectors and processes202010,840,3003D vertical memory array cell structures with individual selectors and processes202010,734,088CMOS anti-fuse cell202010,720,215Methods and apparatus for writing nonvolatile 3D NAND flash memory using multiple-page programming202010,553,2933D NAND array with divided string architecture202010,483,3243D vertical memory array cell structures and processes201910,395,744CMOS anti-fuse cell201910,242,743Method and apparatus for writing nonvolatile memory using multiple-page programming201910,199,104Method and apparatus for providing multi-page read and write using SRAM and nonvolatile memory devices201910,163,509Method and apparatus for storing information using a memory able to perform both NVM and DRAM functions201810,163,916Compact anti-fuse memory cell using CMOS process201810,109,363CMOS anti-fuse cell201810,008,265Method and apparatus for providing three-dimensional integrated nonvolatile memory (NVM) and dynamic random access memory (DRAM) memory device20189,972,392SONOS byte-erasable EEPROM20189,928,911'Method and apparatus for providing multi-page read and write using SRAM and nonvolatile memory devices'20189,793,001'CMOS anti-fuse cell'20179,761,310'Method and apparatus for storing information using a memory able to perform both NVM and DRAM functions'20179,715,933'Dual function hybrid memory cell'20179,704,577'Two transistor SONOS flash memory'20179,063,849'Different types of memory integrated in one chip by using a novel protocol'20158,996,785'NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with serial interface'20158,933,500'EEPROM-based, data-oriented combo NVM design'20158,917,551'Flexible 2T-based fuzzy and certain matching arrays'20148,837,221'Write bias condition for 2T-string NOR flash cell'20148,809,148'EEPROM-based, data-oriented combo NVM design'20148,773,903'High speed high density nand-based 2T-NOR flash memory design'20148,775,719'NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with parallel interface'20148,634,241'Universal timing waveforms sets to improve random access read and write speed of memories'20148,634,254'Single-polycrystalline silicon electrically erasable and programmable memory device of varied gate oxide thickness, using PIP or MIM coupling capacitor for cell size reduction and simultaneous VPP and VNN for write voltage reduction'20148,559,232'DRAM-like NVM memory array and sense amplifier design for high temperature and high endurance operation'20138,531,885'NAND-based 2T2b NOR flash array with a diode connection to cell\'s source node for size reduction using the least number of metal layers'20138,472,251'Single-polycrystalline silicon electrically erasable and programmable nonvolatile memory device'20138,462,553'Cell array for highly-scalable, byte-alterable, two-transistor FLOTOX EEPROM non-volatile memory'20138,455,923'Embedded NOR flash memory process with NAND cell and true logic compatible low voltage device'20138,355,287'Method and apparatus for operation of a NAND-like dual charge retaining transistor NOR flash memory device'20138,345,481'NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory array, and a method of forming a NAND based NMOS NOR flash memory array'20138,335,108'Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND flash array'20128,331,150'Integrated SRAM and FLOTOX EEPROM memory device'20128,295,087'Row-decoder and select gate decoder structures suitable for flashed-based EEPROM operating below +/− 10v BVDS'20128,289,775'Apparatus and method for inhibiting excess leakage current in unselected nonvolatile memory cells in an array'20128,274,829'Row-decoder and source-decoder structures suitable for erase in unit of page, sector and chip of a NOR-type flash operating below +/− 10V BVDS'20128,237,212'Nonvolatile memory with a unified cell structure'20128,233,320'High speed high density NAND-based 2T-NOR flash memory design'20128,149,622'Memory system having NAND-based NOR and NAND flashes and SRAM integrated in one chip for hybrid data, code and cache storage'20128,120,959'NAND string based NAND/NOR flash memory cell, array, and memory device having parallel bit lines and source lines, having a programmable select gating transistor, and circuits and methods for operating same'20128,072,811'NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory array, and a method of forming a NAND based NMOS NOR flash memory array'20117,915,092'Nonvolatile memory with a unified cell structure'20117,855,912'Circuit and method for multiple-level programming, reading, and erasing dual-sided nonvolatile memory cell'20107,830,713'Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND flash array'20107,688,612'Bit line structure for a multilevel, dual-sided nonvolatile memory cell array'20107,636,252'Nonvolatile memory with a unified cell structure'20097,372,736'Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout'20087,349,257'Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations'20087,339,824'Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations'20087,324,384'Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout'20087,289,366'Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout'20077,283,401'Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout'20077,154,783'Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations'20067,149,120'Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations'20067,120,064'Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout'20067,110,302'Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout'20067,102,929'Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout'20067,075,826'Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout'20067,064,978'Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout'20066,906,376'EEPROM cell structure and array architecture'20056,862,223'MONOLITHIC, COMBO NONVOLATILE MEMORY ALLOWING BYTE, PAGE AND BLOCK WRITE WITH NO DISTURB AND DIVIDED-WELL IN THE CELL ARRAY USING A UNIFIED CELL STRUCTURE AND TECHNOLOGY WITH A NEW SCHEME OF DECODER AND LAYOUT'20056,850,438'Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations'20056,839,278'Highly-integrated flash memory and mask ROM array architecture'20056,818,491'Set of three level concurrent word line bias conditions for a NOR type flash memory array'20046,788,611'Flash memory array structure suitable for multiple simultaneous operations'20046,788,612'Flash memory array structure suitable for multiple simultaneous operations'20046,777,292'Set of three level concurrent word line bias conditions for a NOR type flash memory array'20046,757,196'Two transistor flash memory cell for use in EEPROM arrays with a programmable logic device'20046,714,457'Parallel channel programming scheme for MLC flash memory'20046,687,154'Highly-integrated flash memory and mask ROM array architecture'20046,660,585'Stacked gate flash memory cell with reduced disturb conditions'20036,628,563'Flash memory array for multiple simultaneous operations'20036,620,682'Set of three level concurrent word line bias conditions for a nor type flash memory array'20036,584,034'Flash memory array structure suitable for multiple simultaneous operations'20036,574,152'Circuit design for accepting multiple input voltages for flash EEPROM memory operations'20036,556,481'3-step write operation nonvolatile semiconductor one-transistor, nor-type flash EEPROM memory cell'20036,515,910'Bit-by-bit Vt-correction operation for nonvolatile semiconductor one-transistor cell, nor-type flash EEPROM'20036,498,752'Three step write process used for a nonvolatile NOR type EEPROM memory'20026,381,670'Flash memory array having maximum and minimum threshold voltage detection for eliminating over-erasure problem and enhancing write operation'20026,275,417'Multiple level flash memory'20016,262,622'Breakdown-free high voltage input circuitry'20016,240,027'Approach to provide high external voltage for flash memory erase'20016,181,607'Reversed split-gate cell array'20016,166,961'Approach to provide high external voltage for flash memory erase'20006,160,737'Bias conditions for repair, program and erase operations of non-volatile memory'20006,134,150'Erase condition for flash memory'20006,031,765'Reversed split-gate cell array'20006,023,188'Positive/negative high voltage charge pump system'20006,009,022'Node-precise voltage regulation for a MOS memory system'19995,978,277'Bias condition and X-decoder circuit of flash memory array'19995,978,283'Charge pump circuits'19995,953,250'Flash memory array and decoding architecture'19995,930,826'Flash memory protection attribute status bits held in a flash memory array'19995,920,503'Flash memory with novel bitline decoder and sourceline latch'19995,917,757'Flash memory with high speed erasing structure using thin oxide semiconductor devices'19995,914,896'Flash memory with high speed erasing structure using thin oxide and thick oxide semiconductor devices'19995,859,571'Frequency trimmable oscillator and frequency multiplier'19995,856,942'Flash memory array and decoding architecture'19995,856,945'Method for preventing sub-threshold leakage in flash memory cells to achieve accurate reading, verifying, and fast over-erased Vt correction'19995,848,000'Flash memory address decoder with novel latch structure'19985,835,420'Node-precise voltage regulation for a MOS memory system'19985,822,252'Flash memory wordline decoder with overerase repair'19985,796,657'Flash memory with flexible erasing size from multi-byte to multi-block'19985,777,923'Flash memory read/write controller'19985,777,924'Flash memory array and decoding architecture'19985,774,396'Flash memory with row redundancy'19985,768,193'Bit-refreshable method and circuit for refreshing a nonvolatile flash memory'19985,748,538'OR-plane memory cell array for flash memory with bit-based write capability, and methods for programming and erasing the memory cell array'19985,748,545'Memory device with on-chip manufacturing and memory cell defect detection capability'19985,687,121'Flash EEPROM worldline decoder'19975,682,350'Flash memory with divided bitline'19975,646,890'Flexible byte-erase flash memory and decoder'1997

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1997–1999Patents assigned to APLUS INTEGRATED CIRCUITS INC (15)· patent assignee history
1997–2002Based in Taipei, TW· patent location history
1998–2015Patents assigned to APLUS FLASH TECHNOLOGY INC (79)· patent assignee history
1998Based in Hsinchu, TW· patent location history
2000–2001Based in Saratoga, CA, US· patent location history
2001–2020Based in San Jose, CA, US· patent location history
2009–2015Patents assigned to HSU FU-CHANG (28)· patent assignee history
2011–2015Patents assigned to LEE PETER WUNG (23)· patent assignee history
2017–2020Patents assigned to NEO SEMICONDUCTOR INC (14)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
APLUS FLASH TECHNOLOGY INC791998–2015
HSU FU-CHANGself282009–2015
LEE PETER WUNG232011–2015
APLUS INTEGRATED CIRCUITS INC151997–1999
NEO SEMICONDUCTOR INC142017–2020
Locations
LocationPatentsSpan
San Jose, California, US852001–2020
Taipei, TW241997–2002
Saratoga, California, US52000–2001
Hsinchu, TW31998