Inventor

Jon D. Cheek

Inventor

Round Rock, TX, US

Overview

1998–2016

Patent span

Electricity

Primary field (CPC H)

Patents· 68 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices54%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1021%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests6%

H10BElectronic memory devices4%

G01RMeasuring electric variables2%

H01LSemiconductor devices2%

G01NInvestigating or analysing materials by determining their chemical or physical properties1%

G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%

PatentTitleYear

9,276,008'Embedded NVM in a HKMG process'2016 9,054,220'Embedded NVM in a HKMG process'2015 7,422,956'Semiconductor device and method of making semiconductor device comprising multiple stacked hybrid orientation layers'2008 7,410,876'Methodology to reduce SOI floating-body effect'2008 7,253,484'Low-power multiple-channel fully depleted quantum well CMOSFETs'2007 7,238,990'Interlayer dielectric under stress for an integrated circuit'2007 7,235,433'Silicon-on-insulator semiconductor device with silicon layers having different crystal orientations and method of forming the silicon-on-insulator semiconductor device'2007 7,208,383'Method of manufacturing a semiconductor component'2007 7,179,745'Method for offsetting a silicide process from a gate electrode of a semiconductor device'2007 7,091,106'Method of reducing STI divot formation during semiconductor device fabrication'2006 7,074,657'Low-power multiple-channel fully depleted quantum well CMOSFETs'2006 6,833,307'Method for manufacturing a semiconductor component having an early halo implant'2004 6,787,464'Method of forming silicide layers over a plurality of semiconductor devices'2004 6,720,227'Method of forming source/drain regions in a semiconductor device'2004 6,674,135'Semiconductor structure having elevated salicided source/drain regions and metal gate electrode on nitride/oxide dielectric'2004 6,638,829'Semiconductor structure having a metal gate electrode and elevated salicided source/drain regions and a method for manufacture'2003 6,580,122'Transistor device having an enhanced width dimension and a method of making same'2003 6,566,696'Self-aligned VT implant'2003 6,541,321'Method of making transistors with gate insulation layers of differing thickness'2003 6,506,642'Removable spacer technique'2003 6,426,262'Method of analyzing the effects of shadowing of angled halo implants'2002 6,417,539'High density memory cell assembly and methods'2002 6,406,964'Method of controlling junction recesses in a semiconductor device'2002 6,403,979'Test structure for measuring effective channel length of a transistor'2002 6,399,493'Method of silicide formation by silicon pretreatment'2002 6,383,872'Parallel and series-coupled transistors having gate conductors formed on sidewall surfaces of a sacrificial structure'2002 6,372,587'Angled halo implant tailoring using implant mask'2002 6,359,461'Test structure for determining the properties of densely packed transistors'2002 6,358,803'Method of fabricating a deep source/drain'2002 6,346,426'Method and apparatus for characterizing semiconductor device performance variations based on independent critical dimension measurements'2002 6,323,095'Method for reducing junction capacitance using a halo implant photomask'2001 6,316,302'Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant'2001 6,300,205'Method of making a semiconductor device with self-aligned active, lightly-doped drain, and halo regions'2001 6,274,415'Self-aligned Vt implant'2001 6,261,936'Poly gate CD passivation for metrology control'2001 6,261,885'Method for forming integrated circuit gate conductors from dual layers of polysilicon'2001 6,245,649'Method for forming a retrograde impurity profile'2001 6,242,330'Process for breaking silicide stringers extending between silicide areas of different active regions'2001 6,225,201'Ultra short transistor channel length dictated by the width of a sidewall spacer'2001 6,191,446'Formation and control of a vertically oriented transistor channel length'2001 6,180,475'Transistor formation with local interconnect overetch immunity'2001 6,162,694'Method of forming a metal gate electrode using replaced polysilicon structure'2000 6,159,812'Reduced boron diffusion by use of a pre-anneal'2000 6,137,145'Semiconductor topography including integrated circuit gate conductors incorporating dual layers of polysilicon'2000 6,130,454'Gate conductor formed within a trench bounded by slanted sidewalls'2000 6,124,610'Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant'2000 6,118,163'Transistor with integrated poly/metal gate electrode'2000 6,114,211'Semiconductor device with vertical halo region and methods of manufacture'2000 6,110,786'Semiconductor device having elevated gate electrode and elevated active regions and method of manufacture thereof'2000 6,104,077'Semiconductor device having gate electrode with a sidewall air gap'2000 6,104,064'Asymmetrical transistor structure'2000 6,075,417'Ring oscillator test structure'2000 6,074,906'Complementary metal-oxide semiconductor device having source/drain regions formed using multiple spacers'2000 6,037,629'Trench transistor and isolation trench'2000 6,018,180'Transistor formation with LI overetch immunity'2000 5,994,193'Method of making high performance MOSFET with integrated poly/metal gate electrode'1999 5,986,283'Test structure for determining how lithographic patterning of a gate conductor affects transistor properties'1999 5,981,365'Stacked poly-oxide-poly gate for improved silicide formation'1999 5,977,600'Formation of shortage protection region'1999 5,935,766'Method of forming a conductive plug in an interlevel dielectric'1999 5,930,592'Asymmetrical n-channel transistor having LDD implant only in the drain region'1999 5,926,693'Two level transistor formation for optimum silicon utilization'1999 5,904,534'Transistor formation with local interconnect overetch immunity'1999 5,893,739'Asymmetrical P-channel transistor having a boron migration barrier and a selectively formed sidewall spacer'1999 5,866,934'Parallel and series-coupled transistors having gate conductors formed on sidewall surfaces of a sacrificial structure'1999 5,852,310'Multi-level transistor fabrication method with a patterned upper transistor substrate and interconnection thereto'1998 5,780,340'Method of forming trench transistor and isolation trench'1998 5,770,482'Multi-level transistor fabrication method with a patterned upper transistor substrate and interconnection thereto'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1998–2008Patents assigned to ADVANCED MICRO DEVICES INC (63)· patent assignee history

1998–2004Based in Round Rock, TX, US· patent location history

1998–2007Based in Austin, TX, US· patent location history

2006–2007Based in Wallkill, NY, US· patent location history

2007–2016Patents assigned to FREESCALE SEMICONDUCTOR INC (4)· patent assignee history

2007–2016Based in Cedar Park, TX, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
ADVANCED MICRO DEVICES INC	63	1998–2008
FREESCALE SEMICONDUCTOR INC	4	2007–2016

Locations

Location	Patents	Span
Round Rock, Texas, US	54	1998–2004
Cedar Park, Texas, US	6	2007–2016
Wallkill, New York, US	4	2006–2007
Austin, Texas, US	4	1998–2007