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Inventor

Jayprakash Chipalkatti

Inventor
Santa Clara, CA, US

Overview

3→
Patents
2012–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 3 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1043%
H01LSemiconductor devices29%
H05KPrinted circuits14%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%
PatentTitleYear
10,943,882IC package design and methodology to compensate for die-substrate CTE mismatch at reflow temperatures202110,096,534Thermal performance of logic chip in a package-on-package structure20188,102,038'Semiconductor chip attach configuration having improved thermal characteristics'2012

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2012Patents assigned to CHIPALKATTI JAYPRAKASH VIJAY (1)· patent assignee history
2012Patents assigned to SAHASRABUDHE KAPIL HERAMB (1)· patent assignee history
2012Patents assigned to TEXAS INSTRUMENTS INC (1)· patent assignee history
2012Based in Allen, TX, US· patent location history
2018–2021Patents assigned to NVIDIA CORP (2)· patent assignee history
2018Based in Cupertino, CA, US· patent location history
2021Based in Santa Clara, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
NVIDIA CORP22018–2021
CHIPALKATTI JAYPRAKASH VIJAYself12012
SAHASRABUDHE KAPIL HERAMB12012
TEXAS INSTRUMENTS INC12012
Locations
LocationPatentsSpan
Santa Clara, California, US12021
Cupertino, California, US12018
Allen, Texas, US12012