Inventor
Amit S. Kelkar
Inventor
Flower Mound, TX, US
Overview
Patents· 21 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1030%
H01LSemiconductor devices26%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%
B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems7%
H10BElectronic memory devices7%
C25DProcesses for the electrolytic or electrophoretic production of coatings4%
B81BMicrostructural devices or systems, e.g. micromechanical devices2%
C02FTreatment of water, waste water, sewage, or sludge2%
C07CAcyclic or carbocyclic compounds2%
F27BFurnaces, kilns, ovens or retorts in general2%
PatentTitleYear
10,134,689Warpage compensation metal for wafer level packaging technology201810,032,749Three-dimensional chip-to-wafer integration20189,704,809'Fan-out and heterogeneous packaging of electronic components'20179,472,451'Technique for wafer-level processing of QFN packages'20169,331,048'Bonded stacked wafers and methods of electroplating bonded stacked wafers'20169,324,687'Wafer-level passive device integration'20169,219,043'Wafer-level package device having high-standoff peripheral solder bumps'20159,190,391'Three-dimensional chip-to-wafer integration'20159,040,386'Method for varied topographic MEMS cap process'20159,000,587'Wafer-level thin chip integration'20158,970,043'Bonded stacked wafers and methods of electroplating bonded stacked wafers'20158,878,350'Semiconductor device having a buffer material and stiffener'20148,860,222'Techniques for wafer-level processing of QFN packages'20148,124,916'Thermal processing of silicon wafers'2012RE040507'Method of forming pre-metal dielectric film on a semiconductor substrate including first layer of undoped oxide of high ozone:TEOS volume ratio and second layer of low ozone doped BPSG'20086,828,212'Method of forming shallow trench isolation structure in a semiconductor device'20046,824,687'Extraction of phenol from wastewater'20046,709,990'Method for fabrication of a high capacitance interpoly dielectric'20046,495,475'Method for fabrication of a high capacitance interpoly dielectric'20026,489,254'Method of forming pre-metal dielectric film on a semiconductor substrate including first layer of undoped oxide of high ozone:TEOS volume ratio and second layer of low ozone doped BPSG'20026,291,367'Method for depositing a selected thickness of an interlevel dielectric material to achieve optimum global planarity on a semiconductor wafer'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2008Patents assigned to ATMEL CORP (6)· patent assignee history
2001–2004Based in Castle Rock, CO, US· patent location history
2004Patents assigned to ABB LUMMUS GLOBAL INC (1)· patent assignee history
2004Based in Irving, TX, US· patent location history
2004Based in Bloomfield, NJ, US· patent location history
2008–2018Based in Flower Mound, TX, US· patent location history
2012–2018Patents assigned to MAXIM INTEGRATED PRODUCTS (14)· patent assignee history
2012–2015Patents assigned to KELKAR AMIT S (2)· patent assignee history
2012Patents assigned to BILLINGS DAVID E (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MAXIM INTEGRATED PRODUCTS | 14 | 2012–2018 |
| ATMEL CORP | 6 | 2001–2008 |
| KELKAR AMIT Sself | 2 | 2012–2015 |
| ABB LUMMUS GLOBAL INC | 1 | 2004 |
| BILLINGS DAVID E | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Flower Mound, Texas, US | 15 | 2008–2018 |
| Castle Rock, CO, US | 4 | 2001–2004 |
| Irving, Texas, US | 1 | 2004 |
| Bloomfield, New Jersey, US | 1 | 2004 |