Inventor
Erwin Trautmann
Inventor
San Jose, CA, US
Overview
Patents· 5 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices28%
H10DInorganic electric semiconductor devices28%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1028%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1017%
PatentTitleYear
10,879,356Method for making a semiconductor device including enhanced contact structures having a superlattice202010,777,451Semiconductor device including enhanced contact structures having a superlattice20209,972,685Vertical semiconductor devices including superlattice punch through stop layer and related methods20189,406,753'Semiconductor devices including superlattice depletion layer stack and related methods'20169,275,996'Vertical semiconductor devices including superlattice punch through stop layer and related methods'2016Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2016–2020Patents assigned to ATOMERA INC (4)· patent assignee history
2016Patents assigned to MEARS TECHNOLOGIES INC (1)· patent assignee history
2016–2020Based in San Jose, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ATOMERA INC | 4 | 2016–2020 |
| MEARS TECHNOLOGIES INC | 1 | 2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 5 | 2016–2020 |