Inventor

Kamal Sinha

Inventor

Rancho Cordova, CA, US

Overview

60→

Patents

2018–2021

Patent span

Physics

Primary field (CPC G)

Patents· 60 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing29%

G06TImage data processing or generation, in general25%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use16%

G06NComputing arrangements based on specific computational models12%

G09GArrangements or circuits for control of indicating devices using static means to present variable information7%

G06KGraphical data reading3%

H03KPulse technique2%

H03MCoding2%

G06VImage or video recognition or understanding1%

G11CStatic stores1%

PatentTitleYear

11,106,264Processor power management2021 11,099,800Regional adjustment of render rate2021 11,080,810Dynamically reconfigurable memory subsystem for graphics processors2021 11,080,046Instructions and logic to perform floating point and integer operations for machine learning2021 11,074,072Compute optimizations for neural networks using bipolar binary weight2021 11,049,284Compute mechanism for sparse matrix data2021 11,010,163Hierarchical general register file (GRF) for execution block2021 11,010,659Dynamic precision for neural network compute operations2021 10,983,594Sensory enhanced augmented reality and virtual reality device2021 10,970,538Dynamic brightness and resolution control in virtual environments2021 10,956,330Extend GPU/CPU coherency to multi-GPU cores2021 10,955,896Power consumption management for communication bus2021 10,943,325Machine learning sparse computation mechanism2021 10,908,905Efficient multi-context thread distribution2021 10,909,039Data prefetching for graphics data processing2021 10,902,547Compute optimization mechanism for deep neural networks2021 10,901,909Optimizing read only memory surface accesses2021 10,891,707Coordination and increased utilization of graphics processors during inference2021 10,871,966Intelligent thread dispatch and vectorization of atomic operations2020 10,817,012System, apparatus and method for providing a local clock signal for a memory array2020 10,769,748Programmable coarse grained and sparse matrix compute hardware with advanced scheduling2020 10,769,072Avoid cache lookup for cold cache2020 10,762,877System, apparatus and method for reducing voltage swing on an interconnect2020 10,754,809Reducing aging of register file keeper circuits2020 10,748,238Frequent data value compression for graphics processing units2020 10,747,286Dynamic power budget allocation in multi-processor system2020 10,706,498Machine learning sparse computation mechanism2020 10,691,392Regional adjustment of render rate2020 10,691,617Replacement policies for a hybrid hierarchical cache2020 10,591,971Adaptive multi-resolution for graphics2020 10,587,244Pulse triggered flip flop2020 10,580,104Read/write modes for reducing power consumption in graphics processing units2020 10,579,121Processor power management2020 10,558,254Power consumption management for communication bus2020 10,521,271Hybrid low power homogenous grapics processing units2019 10,521,349Extend GPU/CPU coherency to multi-GPU cores2019 10,474,458Instructions and logic to perform floating-point and integer operations for machine learning2019 10,452,397Efficient multi-context thread distribution2019 10,444,817System, apparatus and method for increasing performance in a processor during a voltage ramp2019 10,423,415Hierarchical general register file (GRF) for execution block2019 10,417,734Compute optimization mechanism for deep neural networks2019 10,417,731Compute optimization mechanism for deep neural networks2019 10,409,319System, apparatus and method for providing a local clock signal for a memory array2019 10,410,098Compute optimizations for neural networks2019 10,401,954Sensory enhanced augmented reality and virtual reality device2019 10,403,003Compression mechanism2019 10,353,706Instructions and logic to perform floating-point and integer operations for machine learning2019 10,346,944Machine learning sparse computation mechanism2019 10,346,166Intelligent thread dispatch and vectorization of atomic operations2019 10,324,721Reducing aging of register file keeper circuits2019 10,319,070Dynamic page sizing of page table entries2019 10,304,154Coordination and increased utilization of graphics processors during inference2019 10,262,388Frequent data value compression for graphics processing units2019 10,261,903Extend GPU/CPU coherency to multi-GPU cores2019 10,241,921Avoid cache lookup for cold cache2019 10,186,011Programmable coarse grained and sparse matrix compute hardware with advanced scheduling2019 10,157,444Dynamic page sizing of page table entries2018 10,158,346Pulse triggered flip flop2018 10,152,632Dynamic brightness and resolution control in virtual environments2018 10,102,149Replacement policies for a hybrid hierarchical cache2018

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2018–2021Patents assigned to INTEL CORP (60)· patent assignee history

2018–2021Based in Rancho Cordova, CA, US· patent location history

2019–2021Based in Cordova, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	60	2018–2021

Locations

Location	Patents	Span
Rancho Cordova, California, US	56	2018–2021
Cordova, California, US	4	2019–2021