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Inventor

Leathen Shi

Inventor
Yorktown Heights, NY, US

Overview

53→
Patents
1991–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 53 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1025%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1023%
H10DInorganic electric semiconductor devices20%
H01LSemiconductor devices9%
H10HInorganic light-emitting semiconductor devices having potential barriers3%
Y02PClimate change mitigation technologies in the production or processing of goods3%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
G01RMeasuring electric variables2%
Y10TTechnical subjects covered by former us classification2%
B23KSoldering or unsoldering1%
PatentTitleYear
10,811,305Wafer level integration including design/co-design, structure process, equipment stress management, and thermal management202010,615,139Semiconductor device including built-in crack-arresting film structure202010,211,178Semiconductor device including built-in crack-arresting film structure201910,020,279Semiconductor device including built-in crack-arresting film structure20189,865,469'Epitaxial lift-off process with guided etching'20189,653,308'Epitaxial lift-off process with guided etching'20179,536,853'Semiconductor device including built-in crack-arresting film structure'20179,355,936'Flattened substrate surface for substrate bonding'20168,927,405'Accurate control of distance between suspended semiconductor nanowires and substrate surface'20158,927,968'Accurate control of distance between suspended semiconductor nanowires and substrate surface'20158,877,606'Low cost fabrication of double box back gate silicon-on-insulator wafers with subsequent self aligned shallow trench isolation'20148,778,737'Flattened substrate surface for substrate bonding'20148,637,381'High-k dielectric and silicon nitride box region'20148,586,426'Method of forming isolation structures for SOI devices with ultrathin SOI and ultrathin box'20138,492,838'Isolation structures for SOI devices with ultrathin SOI and ultrathin box'20138,408,262'Adaptive chuck for planar bonding between substrates'20138,030,145'Back-gated fully depleted SOI transistor'20118,017,499'Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)'20117,897,480'Preparation of high quality strained-semiconductor directly-on-insulator substrates'20117,767,546'Low cost fabrication of double box back gate silicon-on-insulator wafers with built-in shallow trench isolation in back gate layer'20107,713,837'Low temperature fusion bonding with high surface energy using a wet chemical treatment'20107,704,815'Method of creating defect free high Ge content (>25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques'20107,691,688'Strained silicon CMOS on hybrid crystal orientations'20107,566,631'Low temperature fusion bonding with high surface energy using a wet chemical treatment'20097,528,056'Low-cost strained SOI substrate for high-performance CMOS technology'20097,521,735'Multiple layer and crystal plane orientation semiconductor substrate'20097,507,989'Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)'20097,488,630'Method for preparing 2-dimensional semiconductor devices for integration in a third dimension'20097,485,518'Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)'20097,445,977'Method of creating defect free high Ge content (> 25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques'20087,402,466'Strained silicon CMOS on hybrid crystal orientations'20087,348,610'Multiple layer and crystal plane orientation semiconductor substrate'20087,235,812'Method of creating defect free high Ge content (>25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques'20077,217,949'Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)'20077,166,521'SOI wafers with 30-100 â„« buried oxide (BOX) created by wafer bonding using 30-100 â„« thin oxide as bonding layer'20077,138,683'Self-aligned SOI with different crystal orientation using WAFER bonding and SIMOX processes'20067,087,965'Strained silicon CMOS on hybrid crystal orientations'20066,911,375'Method of fabricating silicon devices on sapphire with wafer bonding at low temperature'20056,841,831'Fully-depleted SOI MOSFETs with low source and drain resistance and minimal overlap capacitance using a recessed channel damascene gate process'20056,835,633'SOI wafers with 30-100 buried oxide (BOX) created by wafer bonding using 30-100 thin oxide as bonding layer'20046,830,962'Self-aligned SOI with different crystal orientation using wafer bonding and SIMOX processes'20046,686,630'Damascene double-gate MOSFET structure and its fabrication method'20046,660,598'Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region'20036,399,406'Encapsulated MEMS band-pass filter for integrated circuits and method of fabrication thereof'20026,262,464'Encapsulated MEMS brand-pass filter for integrated circuits'20016,224,690'Flip-Chip interconnections using lead-free solders'20015,764,314'Mechanical packaging and thermal management of flat mirror arrays'19985,721,602'Mechanical packaging and thermal management of flat mirror arrays'19985,531,022'Method of forming a three dimensional high performance interconnection package'19965,504,375'Asymmetric studs and connecting lines to minimize stress'19965,424,634'Non-destructive flex testing method and means'19955,371,654'Three dimensional high performance interconnection package'19945,062,896'Solder/polymer composite paste and method'1991

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1991–2020Patents assigned to IBM (52)· patent assignee history
1991–2020Based in Yorktown Heights, NY, US· patent location history
2013–2014Patents assigned to SHI LEATHEN (6)· patent assignee history
2013–2014Patents assigned to DENNARD ROBERT H (3)· patent assignee history
2013–2014Patents assigned to YAU JENG-BANG (3)· patent assignee history
2013Patents assigned to KHATER MARWAN H (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
IBM521991–2020
SHI LEATHENself62013–2014
DENNARD ROBERT H32013–2014
YAU JENG-BANG32013–2014
KHATER MARWAN H22013
Locations
LocationPatentsSpan
Yorktown Heights, New York, US531991–2020