Inventor
Paul M. Harvey
Inventor
Austin, TX, US
Overview
Patents· 23 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1035%
H05KPrinted circuits33%
Y10TTechnical subjects covered by former us classification10%
H10DInorganic electric semiconductor devices6%
Y02PClimate change mitigation technologies in the production or processing of goods6%
H01FMagnets4%
G01LMeasuring force, stress, torque, work, mechanical power, mechanical efficiency, or fluid pressure2%
G01RMeasuring electric variables2%
PatentTitleYear
8,791,372'Reducing impedance discontinuity in packages'20148,631,706'Noise suppressor for semiconductor packages'20148,440,917'Method and apparatus to reduce impedance discontinuity in packages'20138,338,949'System to improve coreless package connections'20128,222,739'System to improve coreless package connections'20128,153,516'Method of ball grid array package construction with raised solder ball pads'20127,911,049'Electrically optimized and structurally protected via structure for high speed signals'20117,816,754'Ball grid array package construction with raised solder ball pads'20107,687,391'Electrically optimized and structurally protected via structure for high speed signals'20107,492,570'Systems and methods for reducing simultaneous switching noise in an integrated circuit'20097,482,654'MOSgated power semiconductor device with source field electrode'20097,390,717'Trench power MOSFET fabrication using inside/outside spacers'20087,388,275'Electronic package with integrated capacitor'20087,368,353'Trench power MOSFET with reduced gate resistance'20087,253,510'Ball grid array package construction with raised solder ball pads'20077,203,608'Impedane measurement of chip, package, and board power supply system using pseudo impulse response'20077,064,412'Electronic package with integrated capacitor'20066,876,088'Flex-based IC package construction employing a balanced lamination'20056,867,121'Method of apparatus for interconnecting a relatively fine pitch circuit layer and adjacent power plane(s) in a laminated construction'20056,153,508'Multi-layer circuit having a via matrix interlayer connection and method for fabricating the same'20006,150,071'Fabrication process for flex circuit applications'20006,140,707'Laminated integrated circuit package'20005,753,976'Multi-layer circuit having a via matrix interlayer connection'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2014Based in Austin, TX, US· patent location history
2000–2008Patents assigned to 3M INNOVATIVE PROPERTIES CO (5)· patent assignee history
2005–2014Patents assigned to IBM (14)· patent assignee history
2008–2009Patents assigned to INT RECTIFIER CORP (3)· patent assignee history
2008–2009Based in Chepstow, GB· patent location history
2012–2014Patents assigned to HARVEY PAUL M (5)· patent assignee history
2012–2014Patents assigned to ZHOU YAPING (4)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 14 | 2005–2014 |
| 3M INNOVATIVE PROPERTIES CO | 5 | 2000–2008 |
| HARVEY PAUL Mself | 5 | 2012–2014 |
| ZHOU YAPING | 4 | 2012–2014 |
| INT RECTIFIER CORP | 3 | 2008–2009 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 20 | 1998–2014 |
| Chepstow, GB | 3 | 2008–2009 |