Inventor
Brent R. Boswell
Inventor
Aloha, OR, US
Overview
Patents· 16 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing63%
H04LTransmission of digital information, e.g. telegraphic communication13%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use13%
G06TImage data processing or generation, in general8%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications4%
PatentTitleYear
10,884,734Generalized acceleration of matrix multiply accumulate operations202110,338,919Generalized acceleration of matrix multiply accumulate operations201910,296,338System, apparatus and method for low overhead control transfer to alternate address space in a processor201910,282,341Method, apparatus and system for configuring a protocol stack of an integrated circuit chip20199,734,116'Method, apparatus and system for configuring a protocol stack of an integrated circuit chip'20178,918,446'Reducing power consumption in multi-precision floating point multipliers'20148,913,740'Method and apparatus for generating an Advanced Encryption Standard (AES) key schedule'20148,787,565'Method and apparatus for generating an advanced encryption standard (AES) key schedule'20148,189,792'Method and apparatus for performing cryptographic operations'20127,366,881'Method and apparatus for staggering execution of an instruction'20086,925,553'Staggering execution of a single packed data instruction using the same circuit'20056,694,426'Method and apparatus for staggering execution of a single packed data instruction using the same circuit'20046,687,810'Method and apparatus for staggering execution of a single packed data instruction using the same circuit'20046,425,073'Method and apparatus for staggering execution of an instruction'20026,230,257'Method and apparatus for staggering execution of a single packed data instruction using the same circuit'20016,055,555'Interface for performing parallel arithmetic and round operations'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2019Patents assigned to INTEL CORP (14)· patent assignee history
2000–2014Based in Beaverton, OR, US· patent location history
2012–2014Patents assigned to CHENNUPATY SRINIVAS (2)· patent assignee history
2012–2021Based in Aloha, OR, US· patent location history
2014–2017Patents assigned to BOSWELL BRENT R (3)· patent assignee history
2017Patents assigned to ANANTHAKRISHNAN AVINASH N (1)· patent assignee history
2019–2021Patents assigned to NVIDIA CORP (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 14 | 2000–2019 |
| BOSWELL BRENT Rself | 3 | 2014–2017 |
| CHENNUPATY SRINIVAS | 2 | 2012–2014 |
| NVIDIA CORP | 2 | 2019–2021 |
| ANANTHAKRISHNAN AVINASH N | 1 | 2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Aloha, OR, US | 8 | 2012–2021 |
| Beaverton, OR, US | 8 | 2000–2014 |